Simulation Results: sysrst_ctrl

 
01/08/2026 02:38:09 DVSim: v1.49.0 sha: 7a3ad34 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.60 %
  • code
  • 98.28 %
  • assert
  • 98.75 %
  • func
  • 92.78 %
  • line
  • 99.42 %
  • branch
  • 99.52 %
  • cond
  • 97.58 %
  • toggle
  • 100.00 %
  • FSM
  • 94.87 %
Validation stages
V1
100.00%
V2
98.80%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
sysrst_ctrl_smoke 7.820s 2112.190us 10 10 100.00
input_output_inverted 10 10 100.00
sysrst_ctrl_in_out_inverted 8.730s 2453.155us 10 10 100.00
combo_detect_ec_rst 5 5 100.00
sysrst_ctrl_combo_detect_ec_rst 7.500s 2418.093us 5 5 100.00
combo_detect_ec_rst_with_pre_cond 5 5 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 6.480s 2501.667us 5 5 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 10.180s 4028.618us 1 1 100.00
csr_rw 5 5 100.00
sysrst_ctrl_csr_rw 7.010s 2064.685us 5 5 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 76.550s 32255.385us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 3.770s 2457.420us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 6.420s 2086.851us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sysrst_ctrl_csr_rw 7.010s 2064.685us 5 5 100.00
sysrst_ctrl_csr_aliasing 3.770s 2457.420us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 25 25 100.00
sysrst_ctrl_combo_detect 363.710s 157930.379us 25 25 100.00
combo_detect_with_pre_cond 97 100 97.00
sysrst_ctrl_combo_detect_with_pre_cond 388.060s 173005.342us 97 100 97.00
auto_block_key_outputs 25 25 100.00
sysrst_ctrl_auto_blk_key_output 627.340s 297091.525us 25 25 100.00
keyboard_input_triggered_interrupt 50 50 100.00
sysrst_ctrl_edge_detect 859.050s 423280.303us 50 50 100.00
pin_output_keyboard_inversion_control 10 10 100.00
sysrst_ctrl_pin_override_test 5.520s 2511.297us 10 10 100.00
pin_input_value_accessibility 10 10 100.00
sysrst_ctrl_pin_access_test 7.790s 2194.492us 10 10 100.00
ec_power_on_reset 10 10 100.00
sysrst_ctrl_ec_pwr_on_rst 12.710s 4767.740us 10 10 100.00
flash_write_protect_output 10 10 100.00
sysrst_ctrl_flash_wr_prot_out 8.850s 2609.703us 10 10 100.00
ultra_low_power_test 24 25 96.00
sysrst_ctrl_ultra_low_pwr 123.800s 1799902.578us 24 25 96.00
sysrst_ctrl_feature_disable 2 2 100.00
sysrst_ctrl_feature_disable 74.140s 33415.200us 2 2 100.00
stress_all 10 10 100.00
sysrst_ctrl_stress_all 136.160s 77410.724us 10 10 100.00
alert_test 10 10 100.00
sysrst_ctrl_alert_test 6.840s 2008.719us 10 10 100.00
intr_test 10 10 100.00
sysrst_ctrl_intr_test 6.980s 2015.809us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sysrst_ctrl_tl_errors 9.340s 2144.896us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sysrst_ctrl_tl_errors 9.340s 2144.896us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sysrst_ctrl_csr_hw_reset 10.180s 4028.618us 1 1 100.00
sysrst_ctrl_csr_rw 7.010s 2064.685us 5 5 100.00
sysrst_ctrl_csr_aliasing 3.770s 2457.420us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 32.440s 10052.872us 5 5 100.00
tl_d_partial_access 12 12 100.00
sysrst_ctrl_csr_hw_reset 10.180s 4028.618us 1 1 100.00
sysrst_ctrl_csr_rw 7.010s 2064.685us 5 5 100.00
sysrst_ctrl_csr_aliasing 3.770s 2457.420us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 32.440s 10052.872us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
sysrst_ctrl_sec_cm 109.030s 42010.929us 5 5 100.00
sysrst_ctrl_tl_intg_err 114.090s 42500.278us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
sysrst_ctrl_tl_intg_err 114.090s 42500.278us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
sysrst_ctrl_stress_all_with_rand_reset 21.240s 6622.705us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)  1 test run
sysrst_ctrl_ultra_low_pwr 63592894623358608442040859864861173117239984319860111766411161913132056559410 655
UVM_INFO @ 2541852695 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
UVM_INFO @ 7591852695 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 7648703188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*]) 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 24102188418529426859433529151668363564185467248577553478521265162594260852248 668
UVM_ERROR @ 13458333870 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:111) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_l2h_expected == 1) Unexpected L2H transition of ec_rst_l_o
UVM_INFO @ 13458333870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 32377507333009256230936492120595541463989423927663047759756467118450014599744 671
UVM_ERROR @ 26864642696 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 26864642696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(8) vs exp(3) +/-* 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 79743293037199963962737333960918395150172345444230964524486071299276540503693 666
UVM_ERROR @ 17593234228 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(8) vs exp(3) +/-4
UVM_INFO @ 17593234228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---