Simulation Results

Simulation Results: otbn

08/08/2026 02:25:00 DVSim: v1.49.0 sha: d313c71 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.69 %

code
87.02 %

assert
97.04 %

func
100.00 %

block
99.37 %

line
99.55 %

branch
95.41 %

toggle
85.49 %

FSM
67.61 %

Validation stages

V1		99.14%
V2		97.55%
V2S		97.87%
V3		40.00%
unmapped		100.00%

115/116 passed

99.14 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	otbn_smoke	35.000s	78.862us	1	1	100.00
single_binary				99	100	99.00
	otbn_single	49.000s	64.721us	99	100	99.00
csr_hw_reset				1	1	100.00
	otbn_csr_hw_reset	35.000s	52.274us	1	1	100.00
csr_rw				5	5	100.00
	otbn_csr_rw	36.000s	25.026us	5	5	100.00
csr_bit_bash				1	1	100.00
	otbn_csr_bit_bash	38.000s	46.960us	1	1	100.00
csr_aliasing				1	1	100.00
	otbn_csr_aliasing	36.000s	116.189us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	otbn_csr_mem_rw_with_rand_reset	40.000s	42.510us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	otbn_csr_rw	36.000s	25.026us	5	5	100.00
	otbn_csr_aliasing	36.000s	116.189us	1	1	100.00
mem_walk				1	1	100.00
	otbn_mem_walk	179.000s	12100.261us	1	1	100.00
mem_partial_access				1	1	100.00
	otbn_mem_partial_access	49.000s	687.669us	1	1	100.00

159/163 passed

97.55 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
reset_recovery				10	10	100.00
	otbn_reset	76.000s	281.179us	10	10	100.00
multi_error				1	1	100.00
	otbn_multi_err	87.000s	773.049us	1	1	100.00
back_to_back				9	10	90.00
	otbn_multi	142.000s	521.223us	9	10	90.00
stress_all				10	10	100.00
	otbn_stress_all	171.000s	967.886us	10	10	100.00
lc_escalation				58	60	96.67
	otbn_escalate	40.000s	35.808us	58	60	96.67
zero_state_err_urnd				5	5	100.00
	otbn_zero_state_err_urnd	8.000s	16.717us	5	5	100.00
sw_errs_fatal_chk				9	10	90.00
	otbn_sw_errs_fatal_chk	31.000s	501.437us	9	10	90.00
alert_test				10	10	100.00
	otbn_alert_test	36.000s	33.539us	10	10	100.00
intr_test				10	10	100.00
	otbn_intr_test	37.000s	22.271us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	otbn_tl_errors	14.000s	202.453us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	otbn_tl_errors	14.000s	202.453us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	otbn_csr_hw_reset	35.000s	52.274us	1	1	100.00
	otbn_csr_rw	36.000s	25.026us	5	5	100.00
	otbn_csr_aliasing	36.000s	116.189us	1	1	100.00
	otbn_same_csr_outstanding	34.000s	58.393us	5	5	100.00
tl_d_partial_access				12	12	100.00
	otbn_csr_hw_reset	35.000s	52.274us	1	1	100.00
	otbn_csr_rw	36.000s	25.026us	5	5	100.00
	otbn_csr_aliasing	36.000s	116.189us	1	1	100.00
	otbn_same_csr_outstanding	34.000s	58.393us	5	5	100.00

V2S

322/329 passed

97.87 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
mem_integrity				25	25	100.00
	otbn_imem_err	52.000s	318.366us	10	10	100.00
	otbn_dmem_err	37.000s	95.560us	15	15	100.00
internal_integrity				16	17	94.12
	otbn_alu_bignum_mod_err	281.000s	923.277us	5	5	100.00
	otbn_controller_ispr_rdata_err	46.000s	54.019us	5	5	100.00
	otbn_mac_bignum_acc_err	40.000s	63.279us	4	5	80.00
	otbn_urnd_err	10.000s	28.881us	2	2	100.00
illegal_bus_access				5	5	100.00
	otbn_illegal_mem_acc	35.000s	16.873us	5	5	100.00
otbn_mem_gnt_acc_err				2	2	100.00
	otbn_mem_gnt_acc_err	35.000s	38.459us	2	2	100.00
otbn_non_sec_partial_wipe				10	10	100.00
	otbn_partial_wipe	34.000s	46.127us	10	10	100.00
tl_intg_err				30	30	100.00
	otbn_sec_cm	413.000s	6287.659us	5	5	100.00
	otbn_tl_intg_err	40.000s	205.672us	25	25	100.00
passthru_mem_tl_intg_err				5	5	100.00
	otbn_passthru_mem_tl_intg_err	67.000s	228.392us	5	5	100.00
prim_fsm_check				5	5	100.00
	otbn_sec_cm	413.000s	6287.659us	5	5	100.00
prim_count_check				5	5	100.00
	otbn_sec_cm	413.000s	6287.659us	5	5	100.00
sec_cm_mem_scramble				1	1	100.00
	otbn_smoke	35.000s	78.862us	1	1	100.00
sec_cm_data_mem_integrity				15	15	100.00
	otbn_dmem_err	37.000s	95.560us	15	15	100.00
sec_cm_instruction_mem_integrity				10	10	100.00
	otbn_imem_err	52.000s	318.366us	10	10	100.00
sec_cm_bus_integrity				25	25	100.00
	otbn_tl_intg_err	40.000s	205.672us	25	25	100.00
sec_cm_controller_fsm_global_esc				58	60	96.67
	otbn_escalate	40.000s	35.808us	58	60	96.67
sec_cm_controller_fsm_local_esc				40	40	100.00
	otbn_imem_err	52.000s	318.366us	10	10	100.00
	otbn_dmem_err	37.000s	95.560us	15	15	100.00
	otbn_zero_state_err_urnd	8.000s	16.717us	5	5	100.00
	otbn_illegal_mem_acc	35.000s	16.873us	5	5	100.00
	otbn_sec_cm	413.000s	6287.659us	5	5	100.00
sec_cm_controller_fsm_sparse				5	5	100.00
	otbn_sec_cm	413.000s	6287.659us	5	5	100.00
sec_cm_scramble_key_sideload				99	100	99.00
	otbn_single	49.000s	64.721us	99	100	99.00
sec_cm_scramble_ctrl_fsm_local_esc				40	40	100.00
	otbn_imem_err	52.000s	318.366us	10	10	100.00
	otbn_dmem_err	37.000s	95.560us	15	15	100.00
	otbn_zero_state_err_urnd	8.000s	16.717us	5	5	100.00
	otbn_illegal_mem_acc	35.000s	16.873us	5	5	100.00
	otbn_sec_cm	413.000s	6287.659us	5	5	100.00
sec_cm_scramble_ctrl_fsm_sparse				5	5	100.00
	otbn_sec_cm	413.000s	6287.659us	5	5	100.00
sec_cm_start_stop_ctrl_fsm_global_esc				58	60	96.67
	otbn_escalate	40.000s	35.808us	58	60	96.67
sec_cm_start_stop_ctrl_fsm_local_esc				40	40	100.00
	otbn_imem_err	52.000s	318.366us	10	10	100.00
	otbn_dmem_err	37.000s	95.560us	15	15	100.00
	otbn_zero_state_err_urnd	8.000s	16.717us	5	5	100.00
	otbn_illegal_mem_acc	35.000s	16.873us	5	5	100.00
	otbn_sec_cm	413.000s	6287.659us	5	5	100.00
sec_cm_start_stop_ctrl_fsm_sparse				5	5	100.00
	otbn_sec_cm	413.000s	6287.659us	5	5	100.00
sec_cm_data_reg_sw_sca				99	100	99.00
	otbn_single	49.000s	64.721us	99	100	99.00
sec_cm_ctrl_redun				12	12	100.00
	otbn_ctrl_redun	37.000s	809.382us	12	12	100.00
sec_cm_pc_ctrl_flow_redun				5	5	100.00
	otbn_pc_ctrl_flow_redun	34.000s	13.501us	5	5	100.00
sec_cm_rnd_bus_consistency				5	5	100.00
	otbn_rnd_sec_cm	55.000s	299.783us	5	5	100.00
sec_cm_rnd_rng_digest				5	5	100.00
	otbn_rnd_sec_cm	55.000s	299.783us	5	5	100.00
sec_cm_rf_base_data_reg_sw_integrity				10	10	100.00
	otbn_rf_base_intg_err	38.000s	101.929us	10	10	100.00
sec_cm_rf_base_data_reg_sw_glitch_detect				5	5	100.00
	otbn_sec_cm	413.000s	6287.659us	5	5	100.00
sec_cm_stack_wr_ptr_ctr_redun				5	5	100.00
	otbn_sec_cm	413.000s	6287.659us	5	5	100.00
sec_cm_rf_bignum_data_reg_sw_integrity				9	10	90.00
	otbn_rf_bignum_intg_err	38.000s	61.272us	9	10	90.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect				5	5	100.00
	otbn_sec_cm	413.000s	6287.659us	5	5	100.00
sec_cm_loop_stack_ctr_redun				5	5	100.00
	otbn_sec_cm	413.000s	6287.659us	5	5	100.00
sec_cm_loop_stack_addr_integrity				4	5	80.00
	otbn_stack_addr_integ_chk	30.000s	17.299us	4	5	80.00
sec_cm_call_stack_addr_integrity				4	5	80.00
	otbn_stack_addr_integ_chk	30.000s	17.299us	4	5	80.00
sec_cm_start_stop_ctrl_state_consistency				7	7	100.00
	otbn_sec_wipe_err	32.000s	16.695us	7	7	100.00
sec_cm_data_mem_sec_wipe				99	100	99.00
	otbn_single	49.000s	64.721us	99	100	99.00
sec_cm_instruction_mem_sec_wipe				99	100	99.00
	otbn_single	49.000s	64.721us	99	100	99.00
sec_cm_data_reg_sw_sec_wipe				99	100	99.00
	otbn_single	49.000s	64.721us	99	100	99.00
sec_cm_write_mem_integrity				9	10	90.00
	otbn_multi	142.000s	521.223us	9	10	90.00
sec_cm_ctrl_flow_count				99	100	99.00
	otbn_single	49.000s	64.721us	99	100	99.00
sec_cm_ctrl_flow_sca				99	100	99.00
	otbn_single	49.000s	64.721us	99	100	99.00
sec_cm_data_mem_sw_noaccess				5	5	100.00
	otbn_sw_no_acc	23.000s	81.822us	5	5	100.00
sec_cm_key_sideload				99	100	99.00
	otbn_single	49.000s	64.721us	99	100	99.00
sec_cm_tlul_fifo_ctr_redun				5	5	100.00
	otbn_sec_cm	413.000s	6287.659us	5	5	100.00

4/10 passed

40.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				4	10	40.00
	otbn_stress_all_with_rand_reset	609.000s	8820.175us	4	10	40.00

unmapped

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	1	100.00
	otbn_smoke_vectorized	31.000s	109.629us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				4 test runs
	otbn_stress_all_with_rand_reset	92942533795352168555075915733400248772966930320239471435482796784138805645214	590	UVM_INFO @ 8820174541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	23641139750299200888839998377399610613283557056438199284624589255844481865156	165	UVM_INFO @ 1082407996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	87575739747783449436946288492234291923821896521234132924088701335282914447842	193	UVM_INFO @ 565006886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	43316074360443698286183916722053070493480437394062070507529213297526802673778	217	UVM_INFO @ 2081821350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error				3 test runs
	otbn_rf_bignum_intg_err	104907174354786664138815544538815032125120869626606018884953661097698098449932	114	UVM_INFO @ 127084247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_sw_errs_fatal_chk	50750551041204012534106253614130163806494399819150308017765738342077051052042	110	UVM_INFO @ 85626593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_mac_bignum_acc_err	93844463363401503568679712594381037213553246465358034330569670982737916367358	129	UVM_INFO @ 83633049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				2 test runs
	otbn_multi	107015742907650768689387574977394261996962657719502442229264806163092089862111	None	~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program) ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize assert bodysize is not None ^^^^^^^^^^^^^^^^^^^^ AssertionError ninja: build stopped: subcommand failed. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
	otbn_single	8743681256310061874010007845107565576711230754896808043374279777960119152041	None	~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program) ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize assert bodysize is not None ^^^^^^^^^^^^^^^^^^^^ AssertionError ninja: build stopped: subcommand failed. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_FATAL (otbn_base_vseq.sv:349) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)				2 test runs
	otbn_stress_all_with_rand_reset	19128690964203046413646518757396209095262138093915699945006453477297223044544	261	UVM_INFO @ 1230293895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	99094099953468762317382688827338609583056063520943636333394590443262936999544	556	UVM_INFO @ 8505145515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:322) [scoreboard] Check failed item.d_data == exp_read_data.val (* [] vs [*]) value for register otbn_reg_block.status				2 test runs
	otbn_escalate	85060553176959693478058881484719176698934216963536952701854387871055000863654	105	UVM_INFO @ 23747356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_escalate	23158738810929205873479823536652264452092611131810253395213306861451462477604	105	UVM_INFO @ 17458412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed				1 test run
	otbn_stack_addr_integ_chk	90247961804368898387501719595106876026727626010392035679257407610620493302848	119	xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,158): (time 17299407 PS) Assertion tb.model_if.NoModelErrs has failed UVM_ERROR @ 17299407 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A UVM_INFO @ 17299407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---