Simulation Results: otbn

 
15/08/2026 02:51:09 DVSim: v1.49.0 sha: e6fb888 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.76 %
  • code
  • 87.03 %
  • assert
  • 97.24 %
  • func
  • 100.00 %
  • block
  • 99.35 %
  • line
  • 99.54 %
  • branch
  • 95.24 %
  • toggle
  • 85.72 %
  • FSM
  • 67.61 %
Validation stages
V1
100.00%
V2
98.77%
V2S
97.26%
V3
30.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 45.000s 68.966us 1 1 100.00
otbn_smoke_vectorized 32.000s 57.256us 1 1 100.00
single_binary 100 100 100.00
otbn_single 95.000s 342.509us 100 100 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 35.000s 198.243us 1 1 100.00
csr_rw 5 5 100.00
otbn_csr_rw 33.000s 142.863us 5 5 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 39.000s 59.829us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 34.000s 39.794us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
otbn_csr_mem_rw_with_rand_reset 36.000s 26.302us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otbn_csr_rw 33.000s 142.863us 5 5 100.00
otbn_csr_aliasing 34.000s 39.794us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 88.000s 997.001us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 90.000s 25126.677us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 67.000s 215.779us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 78.000s 569.617us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 125.000s 1604.290us 10 10 100.00
stress_all 10 10 100.00
otbn_stress_all 666.000s 1745.124us 10 10 100.00
lc_escalation 58 60 96.67
otbn_escalate 30.000s 100.630us 58 60 96.67
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 27.000s 16.912us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 60.000s 158.293us 10 10 100.00
alert_test 10 10 100.00
otbn_alert_test 35.000s 52.290us 10 10 100.00
intr_test 10 10 100.00
otbn_intr_test 33.000s 25.601us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otbn_tl_errors 31.000s 56.165us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otbn_tl_errors 31.000s 56.165us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otbn_csr_hw_reset 35.000s 198.243us 1 1 100.00
otbn_csr_rw 33.000s 142.863us 5 5 100.00
otbn_csr_aliasing 34.000s 39.794us 1 1 100.00
otbn_same_csr_outstanding 34.000s 21.415us 5 5 100.00
tl_d_partial_access 12 12 100.00
otbn_csr_hw_reset 35.000s 198.243us 1 1 100.00
otbn_csr_rw 33.000s 142.863us 5 5 100.00
otbn_csr_aliasing 34.000s 39.794us 1 1 100.00
otbn_same_csr_outstanding 34.000s 21.415us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 33.000s 26.120us 10 10 100.00
otbn_dmem_err 32.000s 63.578us 15 15 100.00
internal_integrity 15 17 88.24
otbn_alu_bignum_mod_err 31.000s 116.523us 4 5 80.00
otbn_controller_ispr_rdata_err 33.000s 116.651us 5 5 100.00
otbn_mac_bignum_acc_err 33.000s 51.923us 5 5 100.00
otbn_urnd_err 30.000s 15.337us 1 2 50.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 29.000s 28.504us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 30.000s 225.169us 2 2 100.00
otbn_non_sec_partial_wipe 7 10 70.00
otbn_partial_wipe 30.000s 148.302us 7 10 70.00
tl_intg_err 30 30 100.00
otbn_sec_cm 1893.000s 8370.564us 5 5 100.00
otbn_tl_intg_err 53.000s 291.730us 25 25 100.00
passthru_mem_tl_intg_err 5 5 100.00
otbn_passthru_mem_tl_intg_err 84.000s 409.314us 5 5 100.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 1893.000s 8370.564us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 1893.000s 8370.564us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 45.000s 68.966us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 32.000s 63.578us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 33.000s 26.120us 10 10 100.00
sec_cm_bus_integrity 25 25 100.00
otbn_tl_intg_err 53.000s 291.730us 25 25 100.00
sec_cm_controller_fsm_global_esc 58 60 96.67
otbn_escalate 30.000s 100.630us 58 60 96.67
sec_cm_controller_fsm_local_esc 40 40 100.00
otbn_imem_err 33.000s 26.120us 10 10 100.00
otbn_dmem_err 32.000s 63.578us 15 15 100.00
otbn_zero_state_err_urnd 27.000s 16.912us 5 5 100.00
otbn_illegal_mem_acc 29.000s 28.504us 5 5 100.00
otbn_sec_cm 1893.000s 8370.564us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 1893.000s 8370.564us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 95.000s 342.509us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 33.000s 26.120us 10 10 100.00
otbn_dmem_err 32.000s 63.578us 15 15 100.00
otbn_zero_state_err_urnd 27.000s 16.912us 5 5 100.00
otbn_illegal_mem_acc 29.000s 28.504us 5 5 100.00
otbn_sec_cm 1893.000s 8370.564us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 1893.000s 8370.564us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 58 60 96.67
otbn_escalate 30.000s 100.630us 58 60 96.67
sec_cm_start_stop_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 33.000s 26.120us 10 10 100.00
otbn_dmem_err 32.000s 63.578us 15 15 100.00
otbn_zero_state_err_urnd 27.000s 16.912us 5 5 100.00
otbn_illegal_mem_acc 29.000s 28.504us 5 5 100.00
otbn_sec_cm 1893.000s 8370.564us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 1893.000s 8370.564us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 95.000s 342.509us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 32.000s 54.950us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 32.000s 51.897us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 68.000s 126.364us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 68.000s 126.364us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 33.000s 29.106us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 1893.000s 8370.564us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 1893.000s 8370.564us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 32.000s 89.578us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 1893.000s 8370.564us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 1893.000s 8370.564us 5 5 100.00
sec_cm_loop_stack_addr_integrity 3 5 60.00
otbn_stack_addr_integ_chk 31.000s 7.762us 3 5 60.00
sec_cm_call_stack_addr_integrity 3 5 60.00
otbn_stack_addr_integ_chk 31.000s 7.762us 3 5 60.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 30.000s 27.820us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 95.000s 342.509us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 95.000s 342.509us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 95.000s 342.509us 100 100 100.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 125.000s 1604.290us 10 10 100.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 95.000s 342.509us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 95.000s 342.509us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 31.000s 36.497us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 95.000s 342.509us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 1893.000s 8370.564us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 3 10 30.00
otbn_stress_all_with_rand_reset 501.000s 2321.918us 3 10 30.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 3 test runs
otbn_stress_all_with_rand_reset 95875250748285630009456799732973352391667276494058232930166301971844783768298 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
otbn_stress_all_with_rand_reset 108279859877066109235596317562496353017474553849795210631698659988984379502443 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
otbn_stress_all_with_rand_reset 52864279988259882704571078053680630656285322503324088557535007685232440768548 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 3 test runs
otbn_stack_addr_integ_chk 50477020844302495465208529112424827137500830131010792181298039365735066721276 135
UVM_ERROR @ 7761903 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 7761903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 15135070522513822684884608175571527356968440995747822310142999240080655380160 117
UVM_ERROR @ 12990534 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 12990534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stack_addr_integ_chk 79489068205267959516576303435222907618720892350346963239729484910285893469987 122
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,158): (time 9426590 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 9426590 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 9426590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 3 test runs
otbn_alu_bignum_mod_err 93361590890349587128590984575014869812588944015401896732036849442459756888266 115
UVM_INFO @ 143144394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_partial_wipe 19311906243858916547896448222446558738971102491088574180061168651983570595522 112
UVM_INFO @ 42677321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_partial_wipe 96747970186333353340492080567615076265097025073214174348360810931653192299859 108
UVM_INFO @ 233487990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
otbn_stress_all_with_rand_reset 36492028671831024291685187784029345909788880915875349065947425914899922652928 552
UVM_INFO @ 3659695603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 31682321344799787390271288302872457040041338499064064346053467854504434383937 162
UVM_INFO @ 471728615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:349) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) 2 test runs
otbn_stress_all_with_rand_reset 38087654619322674731252322889180086649774667398428326637624261086554905602073 198
UVM_INFO @ 972971682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 83283571135046742215286285717315900856114431969543761338425170561191248393250 162
UVM_INFO @ 58488323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,196): Assertion NotRunningWhenLocked_A has failed 1 test run
otbn_urnd_err 79524800506202914864193309098311142626282277053820193531040104254148876833931 116
UVM_ERROR @ 15336723 ps: (otbn_idle_checker.sv:196) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 15336723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,186): Assertion IdleIfLockedAndNotRotatingKeys_A has failed (* cycles, starting * PS) 1 test run
otbn_partial_wipe 88070473800914122887942791222301029467203468703628244922456647368064114210956 118
UVM_ERROR @ 7951384 ps: (otbn_idle_checker.sv:186) [ASSERT FAILED] IdleIfLockedAndNotRotatingKeys_A
UVM_INFO @ 7951384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:322) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status 1 test run
otbn_escalate 84839985336593423372841246936286902380062126349801654236736335272158103344969 114
UVM_INFO @ 5149589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---