Simulation Results: chip

 
22/08/2026 09:08:29 DVSim: v1.49.0 sha: 34ceb5e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.12 %
  • code
  • 77.23 %
  • assert
  • 97.34 %
  • func
  • 98.80 %
  • line
  • 93.99 %
  • branch
  • 94.38 %
  • cond
  • 92.41 %
  • toggle
  • 72.06 %
  • FSM
  • 33.33 %
Validation stages
V1
96.80%
V2
85.92%
V2S
100.00%
V3
82.35%
unmapped
13.64%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 9 9 100.00
chip_sw_example_rom 197.420s 2171.801us 3 3 100.00
chip_sw_example_manufacturer 304.750s 2407.065us 3 3 100.00
chip_sw_example_concurrency 421.170s 2868.415us 3 3 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 881.890s 11309.840us 1 1 100.00
csr_rw 5 5 100.00
chip_csr_rw 1291.830s 13356.481us 5 5 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 2116.290s 16664.198us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 8398.670s 39942.595us 1 1 100.00
csr_mem_rw_with_rand_reset 1 5 20.00
chip_csr_mem_rw_with_rand_reset 1145.810s 13599.802us 1 5 20.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
chip_csr_aliasing 8398.670s 39942.595us 1 1 100.00
chip_csr_rw 1291.830s 13356.481us 5 5 100.00
xbar_smoke 50 50 100.00
xbar_smoke 12.190s 226.825us 50 50 100.00
chip_sw_gpio_out 3 3 100.00
chip_sw_gpio 633.640s 4251.668us 3 3 100.00
chip_sw_gpio_in 3 3 100.00
chip_sw_gpio 633.640s 4251.668us 3 3 100.00
chip_sw_gpio_irq 3 3 100.00
chip_sw_gpio 633.640s 4251.668us 3 3 100.00
chip_sw_uart_tx_rx 5 5 100.00
chip_sw_uart_tx_rx 783.560s 3936.860us 5 5 100.00
chip_sw_uart_rx_overflow 20 20 100.00
chip_sw_uart_tx_rx 783.560s 3936.860us 5 5 100.00
chip_sw_uart_tx_rx_idx1 757.660s 4942.251us 5 5 100.00
chip_sw_uart_tx_rx_idx2 873.630s 4640.676us 5 5 100.00
chip_sw_uart_tx_rx_idx3 789.110s 4250.430us 5 5 100.00
chip_sw_uart_baud_rate 20 20 100.00
chip_sw_uart_rand_baudrate 3333.920s 13126.820us 20 20 100.00
chip_sw_uart_tx_rx_alt_clk_freq 10 10 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1748.130s 7804.765us 5 5 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 1944.790s 13118.570us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 9 10 90.00
chip_padctrl_attributes 923.750s 9763.490us 9 10 90.00
chip_padctrl_attributes 9 10 90.00
chip_padctrl_attributes 923.750s 9763.490us 9 10 90.00
chip_sw_sleep_pin_mio_dio_val 3 3 100.00
chip_sw_sleep_pin_mio_dio_val 474.830s 3230.857us 3 3 100.00
chip_sw_sleep_pin_wake 0 3 0.00
chip_sw_sleep_pin_wake 319.640s 3266.794us 0 3 0.00
chip_sw_sleep_pin_retention 0 3 0.00
chip_sw_sleep_pin_retention 399.560s 3141.700us 0 3 0.00
chip_sw_tap_strap_sampling 20 20 100.00
chip_tap_straps_dev 2148.240s 15564.050us 5 5 100.00
chip_tap_straps_testunlock0 815.740s 7496.397us 5 5 100.00
chip_tap_straps_rma 750.600s 6262.338us 5 5 100.00
chip_tap_straps_prod 789.220s 7348.547us 5 5 100.00
chip_sw_data_integrity 6 6 100.00
chip_sw_data_integrity_escalation 835.000s 5154.708us 6 6 100.00
chip_sw_instruction_integrity 6 6 100.00
chip_sw_data_integrity_escalation 835.000s 5154.708us 6 6 100.00
chip_sw_ast_clk_outputs 3 3 100.00
chip_sw_ast_clk_outputs 1319.630s 7972.194us 3 3 100.00
chip_sw_ast_clk_rst_inputs 0 3 0.00
chip_sw_ast_clk_rst_inputs 3410.640s 14550.103us 0 3 0.00
chip_sw_ast_sys_clk_jitter 24 24 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 6231.950s 19040.031us 3 3 100.00
chip_sw_aes_enc_jitter_en 355.460s 3499.945us 3 3 100.00
chip_sw_edn_entropy_reqs_jitter 1582.280s 7110.913us 3 3 100.00
chip_sw_hmac_enc_jitter_en 402.210s 3026.167us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 2878.500s 12965.106us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 397.700s 3022.362us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 766.210s 4674.786us 3 3 100.00
chip_sw_clkmgr_jitter 408.150s 3063.359us 3 3 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 363.740s 3271.035us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 5 8 62.50
chip_sw_sensor_ctrl_alert 1370.770s 8600.465us 5 5 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 380.730s 3157.719us 0 3 0.00
chip_sw_sensor_ctrl_ast_status 3 3 100.00
chip_sw_sensor_ctrl_status 383.720s 2515.537us 3 3 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 0 3 0.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 380.730s 3157.719us 0 3 0.00
chip_sw_smoketest 48 48 100.00
chip_sw_aes_smoketest 417.040s 2949.221us 3 3 100.00
chip_sw_aon_timer_smoketest 385.110s 2390.892us 3 3 100.00
chip_sw_clkmgr_smoketest 304.030s 2745.395us 3 3 100.00
chip_sw_csrng_smoketest 344.160s 2787.047us 3 3 100.00
chip_sw_entropy_src_smoketest 1871.620s 7206.636us 3 3 100.00
chip_sw_gpio_smoketest 424.450s 3184.923us 3 3 100.00
chip_sw_hmac_smoketest 455.290s 3045.890us 3 3 100.00
chip_sw_kmac_smoketest 429.390s 2591.309us 3 3 100.00
chip_sw_otbn_smoketest 2235.700s 8118.228us 3 3 100.00
chip_sw_pwrmgr_smoketest 681.190s 5781.531us 3 3 100.00
chip_sw_pwrmgr_usbdev_smoketest 684.990s 5323.168us 3 3 100.00
chip_sw_rv_plic_smoketest 376.680s 3355.575us 3 3 100.00
chip_sw_rv_timer_smoketest 416.760s 3068.083us 3 3 100.00
chip_sw_rstmgr_smoketest 339.480s 2486.467us 3 3 100.00
chip_sw_sram_ctrl_smoketest 363.470s 2596.591us 3 3 100.00
chip_sw_uart_smoketest 358.050s 3370.430us 3 3 100.00
chip_sw_otp_smoketest 3 3 100.00
chip_sw_otp_ctrl_smoketest 352.760s 2407.351us 3 3 100.00
chip_sw_rom_functests 3 3 100.00
rom_keymgr_dpe_functest 715.030s 4768.367us 3 3 100.00
chip_sw_boot 0 3 0.00
chip_sw_uart_tx_rx_bootstrap 28800.209s 0.000us 0 3 0.00
chip_sw_secure_boot 3 3 100.00
rom_e2e_smoke 5264.230s 14953.108us 3 3 100.00
chip_sw_rom_raw_unlock 1 3 33.33
rom_raw_unlock 921.090s 10795.115us 1 3 33.33
chip_sw_power_idle_load 3 3 100.00
chip_sw_power_idle_load 791.920s 4307.793us 3 3 100.00
chip_sw_power_sleep_load 1 3 33.33
chip_sw_power_sleep_load 634.990s 9775.336us 1 3 33.33
chip_sw_exit_test_unlocked_bootstrap 0 3 0.00
chip_sw_exit_test_unlocked_bootstrap 13200.198s 0.000us 0 3 0.00
tl_d_oob_addr_access 3 30 10.00
chip_tl_errors 3600.197s 0.000us 3 30 10.00
tl_d_illegal_access 3 30 10.00
chip_tl_errors 3600.197s 0.000us 3 30 10.00
tl_d_outstanding_access 12 12 100.00
chip_csr_aliasing 8398.670s 39942.595us 1 1 100.00
chip_same_csr_outstanding 5664.820s 34185.550us 5 5 100.00
chip_csr_hw_reset 881.890s 11309.840us 1 1 100.00
chip_csr_rw 1291.830s 13356.481us 5 5 100.00
tl_d_partial_access 12 12 100.00
chip_csr_aliasing 8398.670s 39942.595us 1 1 100.00
chip_same_csr_outstanding 5664.820s 34185.550us 5 5 100.00
chip_csr_hw_reset 881.890s 11309.840us 1 1 100.00
chip_csr_rw 1291.830s 13356.481us 5 5 100.00
xbar_base_random_sequence 50 50 100.00
xbar_random 93.450s 2062.251us 50 50 100.00
xbar_random_delay 300 300 100.00
xbar_smoke_zero_delays 7.860s 52.925us 50 50 100.00
xbar_smoke_large_delays 127.600s 11248.017us 50 50 100.00
xbar_smoke_slow_rsp 107.070s 6634.553us 50 50 100.00
xbar_random_zero_delays 48.530s 519.598us 50 50 100.00
xbar_random_large_delays 537.950s 50106.442us 50 50 100.00
xbar_random_slow_rsp 512.480s 30250.314us 50 50 100.00
xbar_unmapped_address 100 100 100.00
xbar_unmapped_addr 61.910s 1180.095us 50 50 100.00
xbar_error_and_unmapped_addr 62.200s 1339.054us 50 50 100.00
xbar_error_cases 100 100 100.00
xbar_error_random 89.050s 2236.365us 50 50 100.00
xbar_error_and_unmapped_addr 62.200s 1339.054us 50 50 100.00
xbar_all_access_same_device 100 100 100.00
xbar_access_same_device 150.340s 3159.322us 50 50 100.00
xbar_access_same_device_slow_rsp 1193.050s 70481.186us 50 50 100.00
xbar_all_hosts_use_same_source_id 50 50 100.00
xbar_same_source 87.920s 2517.862us 50 50 100.00
xbar_stress_all 100 100 100.00
xbar_stress_all 777.900s 17705.320us 50 50 100.00
xbar_stress_all_with_error 703.310s 15660.917us 50 50 100.00
xbar_stress_with_reset 100 100 100.00
xbar_stress_all_with_rand_reset 1351.550s 26628.717us 50 50 100.00
xbar_stress_all_with_reset_error 1116.210s 22723.463us 50 50 100.00
rom_e2e_smoke 3 3 100.00
rom_e2e_smoke 5264.230s 14953.108us 3 3 100.00
rom_e2e_shutdown_output 3 3 100.00
rom_e2e_shutdown_output 6400.780s 42843.325us 3 3 100.00
rom_e2e_shutdown_exception_c 3 3 100.00
rom_e2e_shutdown_exception_c 5933.540s 30263.339us 3 3 100.00
rom_e2e_boot_policy_valid 15 15 100.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 4084.030s 11763.694us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 5616.870s 16476.679us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 5543.830s 16552.288us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 5736.100s 15660.624us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 5456.020s 15470.872us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 4072.920s 12121.116us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 5732.010s 15683.768us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 5746.710s 17444.911us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 5632.660s 16003.522us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 5332.620s 15336.706us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 7308.370s 17738.198us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 9783.720s 24760.027us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 9524.740s 24229.513us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 9710.380s 25812.053us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 9480.420s 23817.888us 1 1 100.00
rom_e2e_sigverify_always 15 15 100.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 7700.200s 28517.042us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 10329.840s 38618.085us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 9790.220s 29556.965us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 9237.590s 29948.595us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 9506.820s 30390.036us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 4437.900s 15890.310us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 6045.030s 27731.273us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 5821.760s 21337.261us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 5594.800s 19606.009us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 4795.520s 13815.883us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 4604.480s 17069.324us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 5969.790s 28307.006us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 5498.190s 19466.917us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 5066.670s 14899.554us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 5460.750s 22349.584us 1 1 100.00
rom_e2e_asm_init 15 15 100.00
rom_e2e_asm_init_test_unlocked0 4475.920s 15742.641us 3 3 100.00
rom_e2e_asm_init_dev 5788.970s 15342.907us 3 3 100.00
rom_e2e_asm_init_prod 5820.480s 15763.330us 3 3 100.00
rom_e2e_asm_init_prod_end 5839.190s 15858.550us 3 3 100.00
rom_e2e_asm_init_rma 5514.830s 15104.559us 3 3 100.00
rom_e2e_keymgr_dpe_init 9 9 100.00
rom_e2e_keymgr_dpe_init_rom_ext_meas 10933.290s 29712.671us 3 3 100.00
rom_e2e_keymgr_dpe_init_rom_ext_no_meas 10851.720s 28988.185us 3 3 100.00
rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas 10842.250s 32121.484us 3 3 100.00
rom_e2e_static_critical 3 3 100.00
rom_e2e_static_critical 5827.270s 16553.395us 3 3 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.195s 0.000us 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.195s 0.000us 0 3 0.00
chip_sw_aes_enc 6 6 100.00
chip_sw_aes_enc 394.480s 2687.851us 3 3 100.00
chip_sw_aes_enc_jitter_en 355.460s 3499.945us 3 3 100.00
chip_sw_aes_entropy 3 3 100.00
chip_sw_aes_entropy 329.040s 2708.838us 3 3 100.00
chip_sw_aes_idle 3 3 100.00
chip_sw_aes_idle 421.980s 2813.700us 3 3 100.00
chip_sw_aes_sideload 3 3 100.00
chip_sw_keymgr_dpe_sideload_aes 3449.000s 12894.480us 3 3 100.00
chip_sw_alert_handler_alerts 0 3 0.00
chip_sw_alert_test 428.120s 2855.250us 0 3 0.00
chip_sw_alert_handler_escalations 3 3 100.00
chip_sw_alert_handler_escalation 790.690s 4708.343us 3 3 100.00
chip_sw_all_escalation_resets 94 100 94.00
chip_sw_all_escalation_resets 958.890s 5847.369us 94 100 94.00
chip_sw_alert_handler_irqs 9 9 100.00
chip_plic_all_irqs_0 971.860s 5076.167us 3 3 100.00
chip_plic_all_irqs_10 623.060s 3593.237us 3 3 100.00
chip_plic_all_irqs_20 757.710s 3554.225us 3 3 100.00
chip_sw_alert_handler_entropy 0 3 0.00
chip_sw_alert_handler_entropy 462.400s 2926.350us 0 3 0.00
chip_sw_alert_handler_crashdump 3 3 100.00
chip_sw_rstmgr_alert_info 2040.910s 10822.440us 3 3 100.00
chip_sw_alert_handler_ping_timeout 3 3 100.00
chip_sw_alert_handler_ping_timeout 765.850s 5411.400us 3 3 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 90 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 391.690s 3112.971us 0 90 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 3 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 408.860s 3091.283us 0 3 0.00
chip_sw_alert_handler_lpg_clock_off 3 3 100.00
chip_sw_alert_handler_lpg_clkoff 2115.260s 8148.550us 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 2206.470s 8276.275us 3 3 100.00
chip_sw_alert_handler_ping_ok 3 3 100.00
chip_sw_alert_handler_ping_ok 1692.770s 8141.641us 3 3 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 0 3 0.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 14400.187s 0.000us 0 3 0.00
chip_sw_aon_timer_wakeup_irq 3 3 100.00
chip_sw_aon_timer_irq 530.250s 3445.471us 3 3 100.00
chip_sw_aon_timer_sleep_wakeup 3 3 100.00
chip_sw_pwrmgr_smoketest 681.190s 5781.531us 3 3 100.00
chip_sw_aon_timer_wdog_bark_irq 3 3 100.00
chip_sw_aon_timer_irq 530.250s 3445.471us 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 988.510s 8493.663us 3 3 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 988.510s 8493.663us 3 3 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 5 5 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 550.870s 6680.518us 5 5 100.00
chip_sw_aon_timer_wdog_lc_escalate 3 3 100.00
chip_sw_aon_timer_wdog_lc_escalate 781.830s 4377.515us 3 3 100.00
chip_sw_clkmgr_idle_trans 12 12 100.00
chip_sw_otbn_randomness 1247.090s 5878.937us 3 3 100.00
chip_sw_aes_idle 421.980s 2813.700us 3 3 100.00
chip_sw_hmac_enc_idle 424.870s 2750.632us 3 3 100.00
chip_sw_kmac_idle 380.680s 2898.500us 3 3 100.00
chip_sw_clkmgr_off_trans 12 12 100.00
chip_sw_clkmgr_off_aes_trans 734.700s 4013.916us 3 3 100.00
chip_sw_clkmgr_off_hmac_trans 598.480s 4279.439us 3 3 100.00
chip_sw_clkmgr_off_kmac_trans 733.510s 4372.138us 3 3 100.00
chip_sw_clkmgr_off_otbn_trans 659.960s 4479.239us 3 3 100.00
chip_sw_clkmgr_off_peri 3 3 100.00
chip_sw_clkmgr_off_peri 1891.820s 10088.573us 3 3 100.00
chip_sw_clkmgr_div 21 21 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 808.320s 3969.306us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 803.320s 5150.853us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 786.380s 3719.510us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 849.190s 5024.075us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 808.390s 4299.416us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 812.240s 5099.586us 3 3 100.00
chip_sw_ast_clk_outputs 1319.630s 7972.194us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 3121.400s 26163.086us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw 6 6 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 786.380s 3719.510us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 849.190s 5024.075us 3 3 100.00
chip_sw_clkmgr_jitter 24 24 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 6231.950s 19040.031us 3 3 100.00
chip_sw_aes_enc_jitter_en 355.460s 3499.945us 3 3 100.00
chip_sw_edn_entropy_reqs_jitter 1582.280s 7110.913us 3 3 100.00
chip_sw_hmac_enc_jitter_en 402.210s 3026.167us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 2878.500s 12965.106us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 397.700s 3022.362us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 766.210s 4674.786us 3 3 100.00
chip_sw_clkmgr_jitter 408.150s 3063.359us 3 3 100.00
chip_sw_clkmgr_extended_range 22 24 91.67
chip_sw_clkmgr_jitter_reduced_freq 345.230s 2785.060us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 6607.500s 25299.399us 3 3 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 359.600s 2672.685us 3 3 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 360.180s 2998.438us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq 2462.790s 11368.770us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 402.450s 3390.064us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 727.560s 4148.242us 3 3 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 28800.201s 0.000us 1 3 33.33
chip_sw_clkmgr_deep_sleep_frequency 3 3 100.00
chip_sw_ast_clk_outputs 1319.630s 7972.194us 3 3 100.00
chip_sw_clkmgr_sleep_frequency 0 3 0.00
chip_sw_clkmgr_sleep_frequency 835.920s 5101.860us 0 3 0.00
chip_sw_clkmgr_reset_frequency 0 3 0.00
chip_sw_clkmgr_reset_frequency 913.970s 7765.692us 0 3 0.00
chip_sw_clkmgr_escalation_reset 94 100 94.00
chip_sw_all_escalation_resets 958.890s 5847.369us 94 100 94.00
chip_sw_clkmgr_alert_handler_clock_enables 3 3 100.00
chip_sw_alert_handler_lpg_clkoff 2115.260s 8148.550us 3 3 100.00
chip_sw_csrng_edn_cmd 3 3 100.00
chip_sw_entropy_src_csrng 3952.360s 23887.244us 3 3 100.00
chip_sw_csrng_fuse_en_sw_app_read 3 3 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 654.860s 4202.314us 3 3 100.00
chip_sw_csrng_lc_hw_debug_en 3 3 100.00
chip_sw_csrng_lc_hw_debug_en_test 1515.220s 9124.298us 3 3 100.00
chip_sw_csrng_known_answer_tests 3 3 100.00
chip_sw_csrng_kat_test 395.740s 2933.316us 3 3 100.00
chip_sw_edn_entropy_reqs 16 16 100.00
chip_sw_csrng_edn_concurrency 14182.800s 41958.993us 10 10 100.00
chip_sw_entropy_src_ast_rng_req 404.220s 3114.309us 3 3 100.00
chip_sw_edn_entropy_reqs 1482.710s 6677.135us 3 3 100.00
chip_sw_entropy_src_ast_rng_req 3 3 100.00
chip_sw_entropy_src_ast_rng_req 404.220s 3114.309us 3 3 100.00
chip_sw_entropy_src_csrng 3 3 100.00
chip_sw_entropy_src_csrng 3952.360s 23887.244us 3 3 100.00
chip_sw_entropy_src_known_answer_tests 3 3 100.00
chip_sw_entropy_src_kat_test 348.130s 3238.850us 3 3 100.00
chip_sw_hmac_enc 6 6 100.00
chip_sw_hmac_enc 361.380s 3149.740us 3 3 100.00
chip_sw_hmac_enc_jitter_en 402.210s 3026.167us 3 3 100.00
chip_sw_hmac_idle 3 3 100.00
chip_sw_hmac_enc_idle 424.870s 2750.632us 3 3 100.00
chip_sw_hmac_all_configurations 3 3 100.00
chip_sw_hmac_oneshot 2924.160s 11764.575us 3 3 100.00
chip_sw_hmac_multistream_mode 0 3 0.00
chip_sw_hmac_multistream 3420.010s 12010.320us 0 3 0.00
chip_sw_i2c_host_tx_rx 9 9 100.00
chip_sw_i2c_host_tx_rx 843.040s 4844.866us 3 3 100.00
chip_sw_i2c_host_tx_rx_idx1 975.760s 5777.113us 3 3 100.00
chip_sw_i2c_host_tx_rx_idx2 954.450s 4812.229us 3 3 100.00
chip_sw_i2c_device_tx_rx 3 3 100.00
chip_sw_i2c_device_tx_rx 682.490s 4343.680us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation 6 6 100.00
chip_sw_keymgr_dpe_key_derivation 3231.880s 12073.747us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 2878.500s 12965.106us 3 3 100.00
chip_sw_keymgr_dpe_sideload_kmac 3 3 100.00
chip_sw_keymgr_dpe_sideload_kmac 3311.730s 12622.024us 3 3 100.00
chip_sw_keymgr_dpe_sideload_aes 3 3 100.00
chip_sw_keymgr_dpe_sideload_aes 3449.000s 12894.480us 3 3 100.00
chip_sw_keymgr_dpe_sideload_otbn 0 3 0.00
chip_sw_keymgr_dpe_sideload_otbn 3600.226s 0.000us 0 3 0.00
chip_sw_kmac_enc 9 9 100.00
chip_sw_kmac_mode_cshake 425.500s 2902.570us 3 3 100.00
chip_sw_kmac_mode_kmac 439.870s 3147.659us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 397.700s 3022.362us 3 3 100.00
chip_sw_kmac_app_keymgr_dpe 3 3 100.00
chip_sw_keymgr_dpe_key_derivation 3231.880s 12073.747us 3 3 100.00
chip_sw_kmac_app_lc 11 15 73.33
chip_sw_lc_ctrl_transition 3461.660s 26812.362us 11 15 73.33
chip_sw_kmac_app_rom 3 3 100.00
chip_sw_kmac_app_rom 809.970s 7999.364us 3 3 100.00
chip_sw_kmac_entropy 3 3 100.00
chip_sw_kmac_entropy 3020.530s 10936.595us 3 3 100.00
chip_sw_kmac_idle 3 3 100.00
chip_sw_kmac_idle 380.680s 2898.500us 3 3 100.00
chip_sw_lc_ctrl_alert_handler_escalation 3 3 100.00
chip_sw_alert_handler_escalation 790.690s 4708.343us 3 3 100.00
chip_sw_lc_ctrl_jtag_access 15 15 100.00
chip_tap_straps_dev 2148.240s 15564.050us 5 5 100.00
chip_tap_straps_rma 750.600s 6262.338us 5 5 100.00
chip_tap_straps_prod 789.220s 7348.547us 5 5 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 3 3 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 414.930s 3220.351us 3 3 100.00
chip_sw_lc_ctrl_init 11 15 73.33
chip_sw_lc_ctrl_transition 3461.660s 26812.362us 11 15 73.33
chip_sw_lc_ctrl_transitions 11 15 73.33
chip_sw_lc_ctrl_transition 3461.660s 26812.362us 11 15 73.33
chip_sw_lc_ctrl_kmac_req 11 15 73.33
chip_sw_lc_ctrl_transition 3461.660s 26812.362us 11 15 73.33
chip_sw_lc_ctrl_key_div 3 3 100.00
chip_sw_keymgr_dpe_key_derivation_prod 3255.710s 11913.238us 3 3 100.00
chip_sw_lc_ctrl_broadcast 68 81 83.95
chip_sw_rram_rma_unlocked 735.950s 10010.400us 0 3 0.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 556.850s 3633.032us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_dev 1096.450s 6201.177us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_prod 1209.700s 6500.201us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_rma 1192.480s 6450.514us 0 3 0.00
chip_sw_lc_ctrl_transition 3461.660s 26812.362us 11 15 73.33
chip_sw_rram_ctrl_lc_rw_en 709.710s 5461.709us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation 3231.880s 12073.747us 3 3 100.00
chip_sw_rom_ctrl_integrity_check 1676.490s 20777.684us 3 3 100.00
chip_sw_sram_ctrl_execution_main 1120.650s 7048.866us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 3121.400s 26163.086us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 808.320s 3969.306us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 803.320s 5150.853us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 786.380s 3719.510us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 849.190s 5024.075us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 808.390s 4299.416us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 812.240s 5099.586us 3 3 100.00
chip_tap_straps_dev 2148.240s 15564.050us 5 5 100.00
chip_tap_straps_rma 750.600s 6262.338us 5 5 100.00
chip_tap_straps_prod 789.220s 7348.547us 5 5 100.00
chip_rv_dm_lc_disabled 211.300s 4671.361us 0 3 0.00
chip_lc_scrap 4 6 66.67
chip_sw_lc_ctrl_rma_to_scrap 658.110s 4904.576us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 885.040s 9099.123us 0 1 0.00
chip_sw_lc_ctrl_test_locked0_to_scrap 694.450s 8333.168us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 1615.380s 26175.115us 2 3 66.67
chip_lc_test_locked 0 6 0.00
chip_sw_lc_walkthrough_testunlocks 3600.200s 0.000us 0 3 0.00
chip_rv_dm_lc_disabled 211.300s 4671.361us 0 3 0.00
chip_sw_lc_walkthrough 3 15 20.00
chip_sw_lc_walkthrough_dev 2600.750s 20463.395us 0 3 0.00
chip_sw_lc_walkthrough_prod 2682.660s 20034.414us 0 3 0.00
chip_sw_lc_walkthrough_prodend 2305.310s 18726.822us 3 3 100.00
chip_sw_lc_walkthrough_rma 1789.040s 14980.635us 0 3 0.00
chip_sw_lc_walkthrough_testunlocks 3600.200s 0.000us 0 3 0.00
chip_sw_lc_ctrl_volatile_raw_unlock 6 9 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 1480.080s 26219.845us 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 1376.520s 25769.138us 2 3 66.67
rom_volatile_raw_unlock 414.510s 5272.702us 2 3 66.67
chip_sw_otbn_op 6 6 100.00
chip_sw_otbn_ecdsa_op_irq 5984.080s 17509.674us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 6231.950s 19040.031us 3 3 100.00
chip_sw_otbn_rnd_entropy 3 3 100.00
chip_sw_otbn_randomness 1247.090s 5878.937us 3 3 100.00
chip_sw_otbn_urnd_entropy 3 3 100.00
chip_sw_otbn_randomness 1247.090s 5878.937us 3 3 100.00
chip_sw_otbn_idle 3 3 100.00
chip_sw_otbn_randomness 1247.090s 5878.937us 3 3 100.00
chip_sw_otbn_mem_scramble 3 3 100.00
chip_sw_otbn_mem_scramble 711.300s 3283.301us 3 3 100.00
chip_otp_ctrl_init 11 15 73.33
chip_sw_lc_ctrl_transition 3461.660s 26812.362us 11 15 73.33
chip_sw_otp_ctrl_keys 9 12 75.00
chip_sw_otbn_mem_scramble 711.300s 3283.301us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation 3231.880s 12073.747us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access 855.490s 4844.970us 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 3600.199s 0.000us 0 3 0.00
chip_sw_otp_ctrl_entropy 9 12 75.00
chip_sw_otbn_mem_scramble 711.300s 3283.301us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation 3231.880s 12073.747us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access 855.490s 4844.970us 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 3600.199s 0.000us 0 3 0.00
chip_sw_otp_ctrl_program 11 15 73.33
chip_sw_lc_ctrl_transition 3461.660s 26812.362us 11 15 73.33
chip_sw_otp_ctrl_program_error 3 3 100.00
chip_sw_lc_ctrl_program_error 932.480s 5485.366us 3 3 100.00
chip_sw_otp_ctrl_hw_cfg0 3 3 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 414.930s 3220.351us 3 3 100.00
chip_sw_otp_ctrl_lc_signals 20 27 74.07
chip_sw_otp_ctrl_lc_signals_test_unlocked0 556.850s 3633.032us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_dev 1096.450s 6201.177us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_prod 1209.700s 6500.201us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_rma 1192.480s 6450.514us 0 3 0.00
chip_sw_lc_ctrl_transition 3461.660s 26812.362us 11 15 73.33
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1500.950s 6908.084us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 3 3 100.00
chip_sw_pwrmgr_full_aon_reset 618.230s 7745.363us 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 0 3 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 313.230s 3188.481us 0 3 0.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 0 3 0.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 356.290s 2645.043us 0 3 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 3 3 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 922.220s 8157.399us 3 3 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 0 3 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 653.700s 4769.096us 0 3 0.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 2137.430s 21357.508us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 6 6 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1763.360s 15168.304us 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 988.510s 8493.663us 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 0 3 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 450.110s 3941.236us 0 3 0.00
chip_sw_pwrmgr_wdog_reset 3 3 100.00
chip_sw_pwrmgr_wdog_reset 826.090s 3891.906us 3 3 100.00
chip_sw_pwrmgr_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_full_aon_reset 618.230s 7745.363us 3 3 100.00
chip_sw_pwrmgr_main_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_main_power_glitch_reset 612.230s 4140.461us 3 3 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 3 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1102.920s 10861.247us 0 3 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 644.610s 6058.258us 3 3 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 3 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 295.860s 2441.309us 0 3 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 3 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 731.130s 8361.615us 0 3 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 6 6 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 1347.850s 7021.938us 3 3 100.00
chip_sw_pwrmgr_all_reset_reqs 1721.820s 9010.231us 3 3 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 3 3 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 3273.450s 23278.068us 3 3 100.00
chip_sw_pwrmgr_sleep_disabled 3 3 100.00
chip_sw_pwrmgr_sleep_disabled 451.710s 3505.141us 3 3 100.00
chip_sw_pwrmgr_escalation_reset 94 100 94.00
chip_sw_all_escalation_resets 958.890s 5847.369us 94 100 94.00
chip_sw_rom_access 3 3 100.00
chip_sw_rom_ctrl_integrity_check 1676.490s 20777.684us 3 3 100.00
chip_sw_rom_ctrl_integrity_check 3 3 100.00
chip_sw_rom_ctrl_integrity_check 1676.490s 20777.684us 3 3 100.00
chip_sw_rstmgr_non_sys_reset_info 9 12 75.00
chip_sw_pwrmgr_all_reset_reqs 1721.820s 9010.231us 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 731.130s 8361.615us 0 3 0.00
chip_sw_pwrmgr_wdog_reset 826.090s 3891.906us 3 3 100.00
chip_sw_pwrmgr_smoketest 681.190s 5781.531us 3 3 100.00
chip_sw_rstmgr_sys_reset_info 3 3 100.00
chip_rv_dm_ndm_reset_req 723.740s 5046.328us 3 3 100.00
chip_sw_rstmgr_cpu_info 3 3 100.00
chip_sw_rstmgr_cpu_info 885.710s 5951.573us 3 3 100.00
chip_sw_rstmgr_sw_req_reset 3 3 100.00
chip_sw_rstmgr_sw_req 596.050s 3548.029us 3 3 100.00
chip_sw_rstmgr_alert_info 3 3 100.00
chip_sw_rstmgr_alert_info 2040.910s 10822.440us 3 3 100.00
chip_sw_rstmgr_sw_rst 3 3 100.00
chip_sw_rstmgr_sw_rst 401.010s 2981.387us 3 3 100.00
chip_sw_rstmgr_escalation_reset 94 100 94.00
chip_sw_all_escalation_resets 958.890s 5847.369us 94 100 94.00
chip_sw_rstmgr_alert_handler_reset_enables 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 2206.470s 8276.275us 3 3 100.00
chip_sw_nmi_irq 3 3 100.00
chip_sw_rv_core_ibex_nmi_irq 919.410s 4475.496us 3 3 100.00
chip_sw_rv_core_ibex_rnd 3 3 100.00
chip_sw_rv_core_ibex_rnd 1055.960s 4886.985us 3 3 100.00
chip_sw_rv_core_ibex_address_translation 3 3 100.00
chip_sw_rv_core_ibex_address_translation 419.740s 3239.224us 3 3 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 0 3 0.00
chip_sw_rv_core_ibex_icache_invalidate 3600.199s 0.000us 0 3 0.00
chip_sw_rv_core_ibex_fault_dump 3 3 100.00
chip_sw_rstmgr_cpu_info 885.710s 5951.573us 3 3 100.00
chip_sw_rv_core_ibex_double_fault 3 3 100.00
chip_sw_rstmgr_cpu_info 885.710s 5951.573us 3 3 100.00
chip_sw_rv_core_ibex_mcounteren_writable 3 3 100.00
chip_sw_rv_core_ibex_mcounteren_writable 332.780s 2610.882us 3 3 100.00
chip_jtag_csr_rw 3 3 100.00
chip_jtag_csr_rw 2956.250s 24148.691us 3 3 100.00
chip_jtag_mem_access 1 3 33.33
chip_jtag_mem_access 2729.730s 23632.184us 1 3 33.33
chip_rv_dm_ndm_reset_req 3 3 100.00
chip_rv_dm_ndm_reset_req 723.740s 5046.328us 3 3 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 3 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 450.810s 2795.047us 0 3 0.00
chip_rv_dm_access_after_wakeup 0 3 0.00
chip_sw_rv_dm_access_after_wakeup 376.050s 2889.657us 0 3 0.00
chip_sw_rv_dm_jtag_tap_sel 5 5 100.00
chip_tap_straps_rma 750.600s 6262.338us 5 5 100.00
chip_rv_dm_lc_disabled 0 3 0.00
chip_rv_dm_lc_disabled 211.300s 4671.361us 0 3 0.00
chip_sw_plic_all_irqs 9 9 100.00
chip_plic_all_irqs_0 971.860s 5076.167us 3 3 100.00
chip_plic_all_irqs_10 623.060s 3593.237us 3 3 100.00
chip_plic_all_irqs_20 757.710s 3554.225us 3 3 100.00
chip_sw_plic_sw_irq 3 3 100.00
chip_sw_plic_sw_irq 300.450s 2299.778us 3 3 100.00
chip_sw_timer 3 3 100.00
chip_sw_rv_timer_irq 305.010s 2894.719us 3 3 100.00
chip_sw_spi_device_flash_mode 3 3 100.00
rom_e2e_smoke 5264.230s 14953.108us 3 3 100.00
chip_sw_spi_device_pass_through 3 3 100.00
chip_sw_spi_device_pass_through 713.060s 5334.876us 3 3 100.00
chip_sw_spi_device_pass_through_collision 0 3 0.00
chip_sw_spi_device_pass_through_collision 415.030s 2875.973us 0 3 0.00
chip_sw_spi_device_tpm 3 3 100.00
chip_sw_spi_device_tpm 530.370s 3180.584us 3 3 100.00
chip_sw_spi_host_tx_rx 3 3 100.00
chip_sw_spi_host_tx_rx 395.590s 3009.136us 3 3 100.00
chip_sw_sram_scrambled_access 6 6 100.00
chip_sw_sram_ctrl_scrambled_access 855.490s 4844.970us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 766.210s 4674.786us 3 3 100.00
chip_sw_sleep_sram_ret_contents 0 6 0.00
chip_sw_sleep_sram_ret_contents_no_scramble 406.140s 3062.026us 0 3 0.00
chip_sw_sleep_sram_ret_contents_scramble 438.620s 2773.778us 0 3 0.00
chip_sw_sram_execution 3 3 100.00
chip_sw_sram_ctrl_execution_main 1120.650s 7048.866us 3 3 100.00
chip_sw_sram_lc_escalation 100 106 94.34
chip_sw_all_escalation_resets 958.890s 5847.369us 94 100 94.00
chip_sw_data_integrity_escalation 835.000s 5154.708us 6 6 100.00
chip_sw_sysrst_ctrl_reset 6 6 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 1347.850s 7021.938us 3 3 100.00
chip_sw_sysrst_ctrl_reset 2328.440s 22765.624us 3 3 100.00
chip_sw_sysrst_ctrl_inputs 3 3 100.00
chip_sw_sysrst_ctrl_inputs 370.580s 3118.550us 3 3 100.00
chip_sw_sysrst_ctrl_outputs 2 3 66.67
chip_sw_sysrst_ctrl_outputs 453.330s 3782.335us 2 3 66.67
chip_sw_sysrst_ctrl_in_irq 3 3 100.00
chip_sw_sysrst_ctrl_in_irq 748.290s 4613.659us 3 3 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 3 3 100.00
chip_sw_sysrst_ctrl_reset 2328.440s 22765.624us 3 3 100.00
chip_sw_sysrst_ctrl_sleep_reset 3 3 100.00
chip_sw_sysrst_ctrl_reset 2328.440s 22765.624us 3 3 100.00
chip_sw_sysrst_ctrl_ec_rst_l 3 3 100.00
chip_sw_sysrst_ctrl_ec_rst_l 4519.300s 20015.760us 3 3 100.00
chip_sw_sysrst_ctrl_flash_wp_l 3 3 100.00
chip_sw_sysrst_ctrl_ec_rst_l 4519.300s 20015.760us 3 3 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 3 6 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 789.300s 6332.987us 3 3 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.195s 0.000us 0 3 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 313.400s 2269.895us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 320.280s 2502.370us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 536.200s 3150.711us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 663.850s 3982.027us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 2031.040s 8159.454us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 9549.110s 32140.136us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 2929.530s 11841.215us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 338.760s 2775.717us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 3 3 100.00
chip_sw_aes_masking_off 465.410s 3405.707us 3 3 100.00
chip_sw_rv_core_ibex_lockstep_glitch 3 3 100.00
chip_sw_rv_core_ibex_lockstep_glitch 259.540s 2198.765us 3 3 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 0 1 0.00
chip_sw_coremark 18000.198s 0.000us 0 1 0.00
chip_sw_power_max_load 3 3 100.00
chip_sw_power_virus 2019.710s 6907.526us 3 3 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 151.470s 2159.939us 0 1 0.00
rom_e2e_jtag_debug_dev 144.620s 2355.214us 0 1 0.00
rom_e2e_jtag_debug_rma 123.520s 1908.147us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 149.620s 2705.620us 0 1 0.00
rom_e2e_jtag_inject_dev 138.280s 2244.355us 0 1 0.00
rom_e2e_jtag_inject_rma 146.340s 2519.230us 0 1 0.00
rom_e2e_self_hash 0 3 0.00
rom_e2e_self_hash 75.599s 0.000us 0 3 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 3 0.00
chip_sw_clkmgr_jitter_frequency 545.840s 3110.368us 0 3 0.00
chip_sw_edn_boot_mode 3 3 100.00
chip_sw_edn_boot_mode 630.630s 2874.871us 3 3 100.00
chip_sw_edn_auto_mode 3 3 100.00
chip_sw_edn_auto_mode 1697.430s 5447.829us 3 3 100.00
chip_sw_edn_sw_mode 3 3 100.00
chip_sw_edn_sw_mode 2229.780s 8875.746us 3 3 100.00
chip_sw_edn_kat 3 3 100.00
chip_sw_edn_kat 478.020s 2297.455us 3 3 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 550.220s 3685.363us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 3 3 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 620.800s 5700.112us 3 3 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 3 3 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 693.100s 4483.768us 3 3 100.00
chip_sw_all_resets 3 3 100.00
chip_sw_pwrmgr_all_reset_reqs 1721.820s 9010.231us 3 3 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 151.470s 2159.939us 0 1 0.00
rom_e2e_jtag_debug_dev 144.620s 2355.214us 0 1 0.00
rom_e2e_jtag_debug_rma 123.520s 1908.147us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 2 3 66.67
chip_sw_rv_dm_access_after_escalation_reset 753.680s 4777.592us 2 3 66.67
chip_sw_plic_alerts 94 100 94.00
chip_sw_all_escalation_resets 958.890s 5847.369us 94 100 94.00
tick_configuration 0 3 0.00
chip_sw_rv_timer_systick_test 7200.190s 0.000us 0 3 0.00
counter_wrap 0 3 0.00
chip_sw_rv_timer_systick_test 7200.190s 0.000us 0 3 0.00
chip_sw_spi_device_output_when_disabled_or_sleeping 0 3 0.00
chip_sw_spi_device_pinmux_sleep_retention 350.400s 3103.505us 0 3 0.00
chip_sw_uart_watermarks 5 5 100.00
chip_sw_uart_tx_rx 783.560s 3936.860us 5 5 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 5459.170s 18420.266us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 3 22 13.64
chip_sw_rstmgr_rst_cnsty_escalation 74.560s 10.200us 0 3 0.00
chip_sw_otp_ctrl_rot_auth_config 2175.680s 17484.278us 0 1 0.00
chip_sw_otp_ctrl_descrambling 472.860s 2845.376us 3 3 100.00
chip_sw_pwrmgr_lowpower_cancel 296.420s 3121.884us 0 3 0.00
chip_sw_pwrmgr_sleep_wake_5_bug 15.816s 0.000us 0 3 0.00
ate_bootstrap_flash_erase 1293.890s 10010.400us 0 3 0.00
ate_bootstrap_one_frame 10800.202s 0.000us 0 3 0.00
ate_bootstrap_disjoint 10800.197s 0.000us 0 3 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 90 test runs
chip_sw_alert_handler_lpg_sleep_mode_alerts 97166008452362800709756131970565447655562041831458887240147339610502769420377 372
UVM_INFO @ 2475.517680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 81474636164224064331803685454521272687363641508533214449543040197448848766689 372
UVM_INFO @ 2488.529606 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 40991954054813405226859870268989423891107334897137185695554867323839782547578 372
UVM_INFO @ 2116.608055 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 115112831148548112750253886871531825297666277134207424548091864395336256560071 372
UVM_INFO @ 3008.767131 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 78739858251875817577858404906966027181121002372541841521408950511010713039937 372
UVM_INFO @ 2328.182634 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 66590967205237472241955770275848229560044222562843982044470227840731229180533 372
UVM_INFO @ 2632.136658 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 107922608418323362065686644833388070980202609378262681617618999117819278349829 372
UVM_INFO @ 2442.293275 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 708315309776978441880465967471368579782521041583812336512889063228407665826 372
UVM_INFO @ 3073.779320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 63738208792079370468558809380560240760885890951432381827201371303510901696427 372
UVM_INFO @ 2939.143726 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 43708349425808154576405525102192201285422441550514530974012886259696309430727 372
UVM_INFO @ 3089.930622 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 80146589980566630236218127590932076380437829454568960699398738445833065950171 372
UVM_INFO @ 2294.042984 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 12916366543791353198546998249133498457989195371011538563798426239081483770273 372
UVM_INFO @ 2850.701440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 113368630475006009309285770553354505125774147381298934313642131504435257835379 372
UVM_INFO @ 2622.612896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 67222826546056686949289237169907583860264108893699970246446668626003631187023 372
UVM_INFO @ 2361.174772 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 7204047137666136307808497821014615734311209177494126149597390987188295357859 372
UVM_INFO @ 2618.488860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 79912679023461205319407661218489117954454447463459308787616388744476886844358 372
UVM_INFO @ 2222.027690 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 49868234824367555207357001072904883058745377602073977127834278485748917344455 372
UVM_INFO @ 3237.519814 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 109670014029275090554274670996809203629829021631644849903499337604943035773370 372
UVM_INFO @ 2629.526190 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 82970752537894178952323764128560171638400121735616260492486015776640251833208 372
UVM_INFO @ 2961.051410 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 8844838583501241051058486588882622283369549706784373354953927269321268538005 372
UVM_INFO @ 2025.978159 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 78774619516621022393701571172903366199441993382939981570226668934061905614086 372
UVM_INFO @ 2399.965500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 84700414922937385408212066713094152023368018849127972359397761413613278333469 372
UVM_INFO @ 2397.209202 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 39983811286136741485525267084763052228865602674555360412570621798809278065551 372
UVM_INFO @ 2478.140141 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 62417789835332814372836228466516161470917451752721309680548954780668991529086 372
UVM_INFO @ 2750.984585 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 93689299228483392873133154605908140557326445227240648482995679369251653005081 372
UVM_INFO @ 3192.439540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 52657609265506211674994497409448039147320426787168862953855658945282541174355 372
UVM_INFO @ 2995.210125 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 60833934190647466517687479087121299499608354889960839900001312888579707838039 372
UVM_INFO @ 2305.577695 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 28114716988970526226980683273535411315540180950216981649299812550340641540383 372
UVM_INFO @ 2521.754360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 12575206034606352877752497379893127476189173080818237886421089125038119921587 372
UVM_INFO @ 2634.239610 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 101462381986951206857666673057288071588343250453951187241340794373090203320117 372
UVM_INFO @ 3012.664912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 53591696197866438636859239868741612266896130906291619644216985965060267872124 372
UVM_INFO @ 2947.014032 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 55517036800422226001557421211402263239902882732310820437444410345852784344003 372
UVM_INFO @ 2490.517356 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 68901948989177934714544527573873695308476066248112003086865824304841859089729 372
UVM_INFO @ 2386.273740 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 113298498077161584653637400506615059331473394416478712056001255871020933932438 372
UVM_INFO @ 3071.585249 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 115532886749916809147049976794700795840150832280910965076282640770457758388692 372
UVM_INFO @ 3303.861994 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 68003936615990288209912435724843108253498406529728333465599436533577791749184 372
UVM_INFO @ 2405.171552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 25124305483723839810646351195884699669521267006352453380909504848042385630301 372
UVM_INFO @ 2628.243150 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 39249980226580413453293203865946202041086792429947576955618184695702121390923 372
UVM_INFO @ 2592.734104 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 96124784074885529765736211512720414627785620514884663505057225177056828185267 372
UVM_INFO @ 2687.574843 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 65765360653894556212814895987887926450968732124382280559103256374431973921321 372
UVM_INFO @ 2615.516635 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 17616316657991770635222841201089973808506999893227773533265929043743752646630 372
UVM_INFO @ 2748.877176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 99317909146373833601079781381439249136960976370059175778042829339747052293523 372
UVM_INFO @ 2675.549146 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 33976457335680832479039976198574234255538299335468098908087395304854724800432 372
UVM_INFO @ 2492.269375 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 35239152538464765444540957178687299821124522561395134483069430810944926322771 372
UVM_INFO @ 2413.841485 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 22371232683164399787873268937444309059364741630547190062064383896898969222934 372
UVM_INFO @ 3017.777449 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 15994741451804027694867444153496893651103755896566750609706274600099955008168 372
UVM_INFO @ 2263.177736 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 54565225089824029917676531866905802423354231628320261719819762365474436907200 372
UVM_INFO @ 2561.958017 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 29807583279060575564779619605840206026283988369312101137240428728753082946096 372
UVM_INFO @ 2806.374120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 57734799489514853832184153098089366186875833563147764554936033015655823944858 372
UVM_INFO @ 2948.332410 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 42328036999207903180577027807630779036808882473840439272746888780909396975231 372
UVM_INFO @ 2695.201901 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 42713058914668076402721591616981968023630538857659731786452491450036029242864 372
UVM_INFO @ 2193.673580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 97702408136081172622659945987797548810135793522062184038849186303419330055991 372
UVM_INFO @ 2741.196018 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 112626509488067717822614566638939329789193456523140435024509997837111792133167 372
UVM_INFO @ 2516.532915 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 70910993045637770481853340184236431799432977034398893628585964880697668885930 372
UVM_INFO @ 2924.174212 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 112818313211558938291139717262722413875598281559918502222615463770682050566659 372
UVM_INFO @ 2818.751480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 106733450636034551566980066325309024292193994655988240016727248050937360277666 372
UVM_INFO @ 2984.998152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 8932858050748802626292942611339881905036634230365701770156412106547485872132 372
UVM_INFO @ 3219.701176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 99790582648276452790728456273686602139041165570757333263041876023002239362750 372
UVM_INFO @ 2999.155367 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 103495777857171813981741879286702057015078175350972015291609185913080335628346 372
UVM_INFO @ 2924.227951 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 68074272502810932949185955814917719571899522717466025035356932895583288945157 372
UVM_INFO @ 2455.691269 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 107098329518120143312436990508217509489357776180191188440677949684914575175723 372
UVM_INFO @ 2793.618995 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 48261835494183453929681683610738716715986872236165745660488279141899240969723 372
UVM_INFO @ 2827.996009 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 104006909778313061261779349194451658948370252595644892553857009020841703287615 372
UVM_INFO @ 2743.269853 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 63307550260843357489327169734913529291671023748306479623248059006703925285989 372
UVM_INFO @ 2645.399758 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 9558195701640141201164722937200478313651707863813852870095779030899498540524 372
UVM_INFO @ 2412.201806 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 107129341794938888456924382714211627542992290734289877637492910621490143565143 372
UVM_INFO @ 2453.613676 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 47733918427680265341712842687898757825273525287009456011389907533814202329046 372
UVM_INFO @ 3051.480817 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 48644739110116378536364559385166638359077713383772264251634230405846503858496 372
UVM_INFO @ 2769.298866 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 3663691935500069492267515543081393151486323300722363264634137100010241944380 372
UVM_INFO @ 2636.980214 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 93871233107863076578943403642530929896008948990632790405235310430478856808801 372
UVM_INFO @ 3117.734722 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 78926423862378031189673408581764349867350185647681150056532055968394374946751 372
UVM_INFO @ 2109.980485 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 36513944932085673139596769412523142018864727884422000366555955130996775663931 372
UVM_INFO @ 2173.086645 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 47249693048104455405138165759415341115818170766186290646063211369348787599195 372
UVM_INFO @ 2802.877624 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 112736469101913484294395807428344501456030860129954102207834732007369300361396 372
UVM_INFO @ 2731.255851 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 87576047518094365454684118993364059591736848903442252951524819943576432190009 372
UVM_INFO @ 2824.567230 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 57532456429972590187533732390462901520860589623579673665328510005254030073614 372
UVM_INFO @ 2663.848160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 25621928053206857894578241519521838161436885708402903479262041263052990310000 372
UVM_INFO @ 2589.650656 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 114152870584931885578176073420822639060208998587382925940611892091991209507981 372
UVM_INFO @ 2832.091212 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 68879279416495222236136184103830654453168576979575878594500878481023398662881 372
UVM_INFO @ 3224.163648 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 86549003483655728165952513371489588949226500168375948329722710158560311412160 372
UVM_INFO @ 2133.927610 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 78690671924630444086002172511764778168679415451699625951933487196915695074843 372
UVM_INFO @ 2833.123330 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 115723712410801914324513003530276045423503875308626009452474951566590990450793 372
UVM_INFO @ 2389.001688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 34629084283039268105276679637881949373740542156452720892186669318175443171630 372
UVM_INFO @ 2562.745645 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 43959759145730004446426194867825729575760822602829673960746096653815550628237 372
UVM_INFO @ 2280.511237 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 71955223992441937097861138121074798129175230497819229422127764079462360839809 372
UVM_INFO @ 2783.416964 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 26619205074892683893929593150799811661035600062256677830860674651616718242894 372
UVM_INFO @ 3106.287018 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 49697096538837663399318041284156719668407650515688598023979305830499293681760 372
UVM_INFO @ 3112.971280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 84717000271356714561405149196694139209003250234891495977063699949457397261679 372
UVM_INFO @ 2666.970011 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 26815246008358205384466447149760650737816764545456490174047714803984529775526 372
UVM_INFO @ 2359.375426 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 54049015554992523099425345851660993282625767491882161545096068835813295038603 372
UVM_INFO @ 2392.630428 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:254) scoreboard [scoreboard] alert fatal has unexpected signal int error 47 test runs
chip_sw_sleep_pin_wake 38849578446644071430205037984140718197566244565983149901250040746574675147171 381
UVM_INFO @ 3011.603154 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_pin_retention 2061912099091832488974772003821917939398985456834929830711614499661900277232 378
UVM_INFO @ 2742.144552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pinmux_sleep_retention 51993056390466852558461113279715351522370632953110478168888036592332487647904 373
UVM_INFO @ 2298.389718 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_reset_reqs 48926971816243057412458425387106110531289079943308816277547897983751330324185 391
UVM_INFO @ 6883.198662 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 46944469551202614464126579506399348943482695593083307392618498344399176449418 376
UVM_INFO @ 3941.235688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_por_reset 46311307924488053457137244421863887878463609442699759187424973720025123083215 387
UVM_INFO @ 4769.096164 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_no_scramble 99466393470389541688210960533020234427971584768871252821433449072193362085930 376
UVM_INFO @ 2606.818098 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_scramble 11935169460040600335664299929828209090231766536282123819825806795877531381081 380
UVM_INFO @ 2773.777588 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 24900586005514435679685506335120787776264800912311728624637804922215426105612 371
UVM_INFO @ 2100.304488 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_sleep_frequency 17679030798419991976496338314298149969037329952954537528781962570534288167195 406
UVM_INFO @ 5101.860068 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_wake_ups 76268417147875385792797177030089405206447506951026702679634579202578074485187 373
UVM_INFO @ 2645.042972 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_lowpower_cancel 52521494600859551587781469995714265763717062917032669333068554346013126307798 371
UVM_INFO @ 3121.884354 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_wake_ups 59470752544268976277712447085805989665371678469786573183133892317579573461805 372
UVM_INFO @ 2842.486752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rv_dm_access_after_wakeup 74592446378886892009479120886368252578540317835769710490450545269383959158631 383
UVM_INFO @ 2822.065560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_sleep_load 36582357199847339239492429940128420560571174393125436126179990673637278460023 386
UVM_INFO @ 3838.001832 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_pin_wake 6766933511851476621842569539761779459863556541949811033442999609968154574532 381
UVM_INFO @ 2523.424464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_pin_retention 108074720017220982366085767198134932880790962789984073854103926838795672693461 378
UVM_INFO @ 3141.699502 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pinmux_sleep_retention 54101920473176355939348941828338528219072742587109373990827018021452117996522 373
UVM_INFO @ 3103.505290 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_reset_reqs 17065174517013560323502918724575637151065590782261868373385255658920927944010 391
UVM_INFO @ 6094.609596 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 18152854456281008514143994308973436815548088299719320924032224987445109572040 376
UVM_INFO @ 3111.984708 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_por_reset 97565712248962659987173098804158800106246955292448420442232668831124792181082 387
UVM_INFO @ 4244.884747 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 70318548967939039164090820496796633619090271532538552913034842095486263707434 402
UVM_INFO @ 7201.788486 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_no_scramble 83716826594634996057141520314441697208501813735000273066452079578129275547316 376
UVM_INFO @ 3062.025662 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_scramble 62550737481157416656653180629777855056890900489641372236449312045106552234285 380
UVM_INFO @ 3029.491386 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 82295353188131983524214142010247747871506614658162744358668055020940689351204 371
UVM_INFO @ 3157.718724 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_sleep_frequency 37068062959772421137430889874987246136369059871853462196683465466018743845654 406
UVM_INFO @ 4660.546556 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_wake_ups 71052438136044428429503348178135360063729430727477977391437652251139045141477 373
UVM_INFO @ 3238.043276 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_lowpower_cancel 53216246996215852246559524769780475290772500467979490665133039160135437670253 371
UVM_INFO @ 2824.797224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_wake_ups 40120359575027406282470601780286904087523431346621724183839177442369150651561 372
UVM_INFO @ 3188.480616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rv_dm_access_after_wakeup 14260584114646888774943099860163712432256358774652894136029385833345651997226 383
UVM_INFO @ 2889.657318 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_pin_wake 43268877701023892890993106957163144120144122026781452125056509934477095604274 381
UVM_INFO @ 3266.794340 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_pin_retention 65917935859515524708729275473724355851824916080895141078545021714169668842913 378
UVM_INFO @ 3384.247182 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pinmux_sleep_retention 13181261664674412585201216736937781880118071492705776173701177043339294230105 373
UVM_INFO @ 2355.823166 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_reset_reqs 89462889922569805803270869949902505147855521513671905150969492501656896697836 391
UVM_INFO @ 8361.615456 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 19001464451494237961373631284102595926422594184914779022792290499482010006997 376
UVM_INFO @ 3726.651184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_por_reset 43541224102573351349798847408559338831704087385820741065303525892958116691259 387
UVM_INFO @ 5210.286878 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 16452861311275298949692290383232824081719024506369933295525403051622374775099 378
UVM_INFO @ 3439.834224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_pings 63477402245350138757363734397007902687541745911403173027054427183700432315842 373
UVM_INFO @ 3091.283432 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_no_scramble 14412927048437713216211878463754064393104417038209378818488134128647247741495 376
UVM_INFO @ 2961.227562 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_scramble 55099702658303600410849108205114718783835424282714996269049288139441825529083 380
UVM_INFO @ 3026.223378 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 11640076660095196320968078143610375951370624109681203831689694149999458875941 371
UVM_INFO @ 2818.185024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_sleep_frequency 90867771773562283260478135554929839459200146744169888296503747906784308428998 406
UVM_INFO @ 4775.043338 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_wake_ups 98945267506315598386343701626793706327496456582812341629832710653515176777470 373
UVM_INFO @ 2571.918414 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_lowpower_cancel 88658014764979436978448979523097396533774239492379764418530922890810108359636 371
UVM_INFO @ 3142.661808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_wake_ups 27389833566856169254145410170056152000199165419961269462487119716495414578141 372
UVM_INFO @ 3027.178330 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rv_dm_access_after_wakeup 55625308125416629163926912060722582815131614618439140649670704298517248836053 383
UVM_INFO @ 2915.550048 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_sleep_load 13454029869665316468791807131227259314060354759862072807460895960648680886 386
UVM_INFO @ 3792.510824 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 34 test runs
chip_sw_uart_tx_rx_bootstrap 31478921923820500298460193222503991301690150417333702012609847172954033312300 None
chip_sw_exit_test_unlocked_bootstrap 73066467285075062058694142367877565237812492992461648380672899917527565043632 None
chip_sw_lc_walkthrough_testunlocks 57079904310601295910793864682401571935643703254318476470063414846181052102150 None
chip_sw_rv_timer_systick_test 11951911776642959487102339954119906385842459111205603102686595604741392351090 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 12961538285235191680390116900030511006863094867436198078172780541775302841838 None
chip_sw_alert_handler_reverse_ping_in_deep_sleep 32147795615281894768190524800781094621942650479170795208015429358015129308542 None
chip_sw_keymgr_dpe_sideload_otbn 74408721035422129451515981764725282064398879815747124228739873483980262920826 None
chip_sw_coremark 25327317597229247842613777676407382760958487515059231376851998733431403796330 None
chip_sw_rv_core_ibex_icache_invalidate 22700997242713493309148582176463954523665212111729113613406321519939673512164 None
ate_bootstrap_one_frame 11484900678268500451271280758626862205164533878646397496359727361139289001620 None
ate_bootstrap_disjoint 112721198131176803638491614143948592137521928610737463529539207877170311823710 None
chip_sw_uart_tx_rx_bootstrap 38207024602945306806990047353860108815120908729375814992322430147215490081410 None
chip_sw_exit_test_unlocked_bootstrap 46651296443760277833390975048583209173744478871044721213089289540039036150337 None
chip_sw_lc_walkthrough_testunlocks 14226185159959337522930803616254685022294766669980560216022773267989571219668 None
chip_sw_rv_timer_systick_test 5645789592615276923993401818569632086463562513296833877894118315195140747679 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 36369070460110201507549063726146726819218184519777755419332443275739570593695 None
chip_sw_keymgr_dpe_sideload_otbn 89897401763437980745027658831155330979361344621060541347754851031823160862130 None
chip_tl_errors 4162004145393176576344125661770973523294711121928255600141844469116474970843 None
chip_sw_rv_core_ibex_icache_invalidate 97317811398512153110578775997443756022737188467149406810557779336249726332889 None
chip_sw_csrng_edn_concurrency_reduced_freq 104656704671159111699909066211074499981095673744862098566391170182439941742436 None
ate_bootstrap_one_frame 7049230325950545554885746462134226147354439073717354491366893423504698503960 None
ate_bootstrap_disjoint 99973666493484310056534675442703352533263067552767342246887616039118775665025 None
chip_sw_uart_tx_rx_bootstrap 104282338971105775796887733326642694517336859279815071004171452869040104307394 None
chip_sw_exit_test_unlocked_bootstrap 112454354617400133008629071205040284221392095333966196239756367599138789488422 None
chip_sw_lc_walkthrough_testunlocks 59138345274072192580682593822684266408803483527456479939117666093127957653698 None
chip_sw_rv_timer_systick_test 111611896166008887295644741977033882876059301307823097385432420486489110527836 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 22792745819038448173233672960181777820411347050530017911775262986338333512629 None
chip_sw_alert_handler_reverse_ping_in_deep_sleep 75504810167919424758133454751998906418740146689575378629190034018760041457510 None
chip_sw_keymgr_dpe_sideload_otbn 22569783873480179753463852637265375883966849056401401239809416463392982895356 None
chip_sw_rv_core_ibex_icache_invalidate 89278238649684779036892542468683109857036207383025788428805635428567131278999 None
chip_sw_csrng_edn_concurrency_reduced_freq 63589243107975649055079908270764135322943642483811417932179263535194313094422 None
ate_bootstrap_one_frame 104382236746499237968116880891692088454370139775061053897111261852664662748799 None
ate_bootstrap_disjoint 85779838961053654927190865292712332495277457217684717845814401643915009566663 None
chip_tl_errors 105267308060796923898944954239760807118781995493420172639700533976747834700761 None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:689) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 28 test runs
chip_tl_errors 21009252037528927066872999990729211359444802716416860657316588696990783130659 281
TL item was: req: (cip_tl_seq_item@33257) { a_addr: 'h10554 a_data: 'h9c6b04eb a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hb a_opcode: 'h4 a_user: 'h1927f d_param: 'h0 d_source: 'hb d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1769.734066 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 77051950812120436638453880697681959601049262239925078531970040216586963720634 285
TL item was: req: (cip_tl_seq_item@32093) { a_addr: 'h10670 a_data: 'he089cce8 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h18 a_opcode: 'h4 a_user: 'h18a23 d_param: 'h0 d_source: 'h18 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2003.718024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 67606217079939764986242414012326769884423057980868473651581180382038876768777 281
TL item was: req: (cip_tl_seq_item@31661) { a_addr: 'h10578 a_data: 'h7b4fb700 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1d a_opcode: 'h4 a_user: 'h192b5 d_param: 'h0 d_source: 'h1d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2432.645232 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 34765065434680866366224659657927416342984968051036928692053678931320282194188 281
TL item was: req: (cip_tl_seq_item@32661) { a_addr: 'h104f8 a_data: 'h2c99e933 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2c a_opcode: 'h4 a_user: 'h1a558 d_param: 'h0 d_source: 'h2c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2041.589474 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 67609306979328870122297282019645636613052692163061702122571852202792628214523 285
TL item was: req: (cip_tl_seq_item@31751) { a_addr: 'h1060c a_data: 'h7181d682 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h34 a_opcode: 'h4 a_user: 'h1868a d_param: 'h0 d_source: 'h34 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1908.951225 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 23494480227717595965991435801289858370322548909280706006700062618179453995505 281
TL item was: req: (cip_tl_seq_item@32193) { a_addr: 'h10570 a_data: 'h2241e5ee a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3c a_opcode: 'h4 a_user: 'h1865c d_param: 'h0 d_source: 'h3c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1842.112330 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 2867159934244867193622755101655679378400931415410467656881747727841363101473 285
TL item was: req: (cip_tl_seq_item@32233) { a_addr: 'h10504 a_data: 'h780ceca8 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h18 a_opcode: 'h4 a_user: 'h19e49 d_param: 'h0 d_source: 'h18 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1958.291960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 40092812168326912944263896375060777759013082979959566008202896321163728423438 281
TL item was: req: (cip_tl_seq_item@33599) { a_addr: 'h1077c a_data: 'he474c26f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h22 a_opcode: 'h4 a_user: 'h19509 d_param: 'h0 d_source: 'h22 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2135.330139 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 62076069368785275050797889590079839486215550985055239425623797590419716626272 281
TL item was: req: (cip_tl_seq_item@32311) { a_addr: 'h10594 a_data: 'h27952f98 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h28 a_opcode: 'h4 a_user: 'h18a38 d_param: 'h0 d_source: 'h28 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2450.690975 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 2699191845529934496688731508368680368056263903346032794708108504327716550577 281
TL item was: req: (cip_tl_seq_item@31803) { a_addr: 'h10600 a_data: 'ha1630ea0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1c a_opcode: 'h4 a_user: 'h19eb1 d_param: 'h0 d_source: 'h1c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2198.230300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 19988932413433364786593400264398349966499823627872115970508284445730980698512 281
TL item was: req: (cip_tl_seq_item@34189) { a_addr: 'h10594 a_data: 'h61987f20 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hd a_opcode: 'h4 a_user: 'h18a4f d_param: 'h0 d_source: 'hd d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2166.357318 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 16012105918884370860684978170341160273491541543644046227247949377177924231642 281
TL item was: req: (cip_tl_seq_item@31853) { a_addr: 'h104a8 a_data: 'hbae133d1 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h8 a_opcode: 'h4 a_user: 'h1a942 d_param: 'h0 d_source: 'h8 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2034.712106 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 101574694688019404419996600386644518422628861661862451134367105610583694559240 281
TL item was: req: (cip_tl_seq_item@32453) { a_addr: 'h105a8 a_data: 'h1e127797 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hb a_opcode: 'h4 a_user: 'h1ae39 d_param: 'h0 d_source: 'hb d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2013.888249 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 20674780585444142245136078060929653369832206714630901228875628860091010255047 281
TL item was: req: (cip_tl_seq_item@34419) { a_addr: 'h1072c a_data: 'h7939939b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2 a_opcode: 'h4 a_user: 'h19967 d_param: 'h0 d_source: 'h2 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1756.883128 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 49598757842431115670553624177068248065043350186739223249249063814937548278156 281
TL item was: req: (cip_tl_seq_item@31861) { a_addr: 'h10724 a_data: 'hef8fac34 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h23 a_opcode: 'h4 a_user: 'h18d83 d_param: 'h0 d_source: 'h23 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1985.103762 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 42949713765089566806445580450559300080946831546166203224722851225843250293118 281
TL item was: req: (cip_tl_seq_item@33499) { a_addr: 'h107d8 a_data: 'h748bf551 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h35 a_opcode: 'h4 a_user: 'h1b1d5 d_param: 'h0 d_source: 'h35 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1930.869992 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 61368318002726549780368199276511580053933320155534169106209426458817250337678 281
TL item was: req: (cip_tl_seq_item@42187) { a_addr: 'h10698 a_data: 'h769670cf a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hf a_opcode: 'h4 a_user: 'h19e43 d_param: 'h0 d_source: 'hf d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1983.992776 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 19993798184498132657259881774770241833221932096250450223559758105577843157721 281
TL item was: req: (cip_tl_seq_item@40341) { a_addr: 'h10568 a_data: 'h1c70e649 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h8 a_opcode: 'h4 a_user: 'h1b631 d_param: 'h0 d_source: 'h8 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2463.480060 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 25990696457087669303427686297483329997421635770895199171494289202447271815133 281
TL item was: req: (cip_tl_seq_item@32167) { a_addr: 'h10568 a_data: 'he60ddf6d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h19 a_opcode: 'h4 a_user: 'h1b61c d_param: 'h0 d_source: 'h19 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2119.186925 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 23376103736805684059997557363523771918242730416584851536802276981657900681649 281
TL item was: req: (cip_tl_seq_item@32293) { a_addr: 'h1068c a_data: 'h591593c7 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h34 a_opcode: 'h4 a_user: 'h1b626 d_param: 'h0 d_source: 'h34 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1887.114000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 38689713872264741581227478260946377913362088940509805296368627049670608684190 281
TL item was: req: (cip_tl_seq_item@34715) { a_addr: 'h10518 a_data: 'hf15481bf a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3a a_opcode: 'h4 a_user: 'h1a2ab d_param: 'h0 d_source: 'h3a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1566.552455 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 92362500660971327422167897307239119277660986053545314209883527120112461398058 281
TL item was: req: (cip_tl_seq_item@33385) { a_addr: 'h105b4 a_data: 'hdc69d065 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h14 a_opcode: 'h4 a_user: 'h192d8 d_param: 'h0 d_source: 'h14 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1679.944035 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 113531138850273134971480027911621263338929477529505775136230929457423122397534 281
TL item was: req: (cip_tl_seq_item@41197) { a_addr: 'h10458 a_data: 'hcfc9b416 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h34 a_opcode: 'h4 a_user: 'h18d69 d_param: 'h0 d_source: 'h34 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2026.892388 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 63725008025724186969688003328208173369806000115919886612560593904266912772360 281
TL item was: req: (cip_tl_seq_item@33355) { a_addr: 'h10374 a_data: 'h63f71198 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hd a_opcode: 'h4 a_user: 'h192e4 d_param: 'h0 d_source: 'hd d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1761.304056 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 19551024485886369815578371102248577782273841998090704159690757206156793819713 281
TL item was: req: (cip_tl_seq_item@38195) { a_addr: 'h104fc a_data: 'h89eb67ed a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2e a_opcode: 'h4 a_user: 'h1a999 d_param: 'h0 d_source: 'h2e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1970.373858 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 108051955757710631214246455382861035398117410401993946209771146216035605666212 281
TL item was: req: (cip_tl_seq_item@33599) { a_addr: 'h10654 a_data: 'h5e4d199f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3d a_opcode: 'h4 a_user: 'h19e1c d_param: 'h0 d_source: 'h3d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1878.171216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 52721090861770911181246619264433906701118669747675806827034962823725758267538 281
TL item was: req: (cip_tl_seq_item@35349) { a_addr: 'h10794 a_data: 'h5bf08365 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1e a_opcode: 'h4 a_user: 'h1811c d_param: 'h0 d_source: 'h1e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2222.489102 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 48863162684648440247321002031965509006198158925229067468066548310320081264625 281
TL item was: req: (cip_tl_seq_item@34029) { a_addr: 'h1051c a_data: 'hd89590b1 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h29 a_opcode: 'h4 a_user: 'h1ae07 d_param: 'h0 d_source: 'h29 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2206.270799 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 9 test runs
chip_sw_lc_walkthrough_dev 30802864170205590488069064634685490384684680417605397519438671315123144017489 432
UVM_INFO @ 17990.884314 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 59327604979051694768213059850914971622223057049619492833488095947527972299196 432
UVM_INFO @ 19198.246576 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 79206095085149638770606057151020027617848290202343989562763628854698330673857 404
UVM_INFO @ 11305.914142 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_dev 71476056510419683887961635326475408697708624716868872364246502185756402756000 432
UVM_INFO @ 20463.394904 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 98264426240355935272404334308036962023624609359866995381103532533573577978902 432
UVM_INFO @ 20486.322352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 83345367609938719645091244591815384989430858362054592489979143658913256319098 404
UVM_INFO @ 14980.635442 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_dev 52037192938200052862317345964535585557548903340729812038917242477447601340929 432
UVM_INFO @ 17354.691986 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 13474084203970704787708413749772425755777499546655558830526340648701479129021 432
UVM_INFO @ 20034.414350 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 43028616125950113341264834592343479349261880859689691321186186899770638534904 404
UVM_INFO @ 12647.241896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access 7 test runs
chip_sw_otp_ctrl_rot_auth_config 16564345031386679768732222964667346879485507345781028224749291040645385560938 379
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 37050536309570200066379647292991712254511661455668032701714170456188208548338 396
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 82025646046831157383451303145643165204563570612079142411679949007228421662729 374
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 18052318082614472562595350991274831294813927753583079203148877246419941071318 372
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 26187675189068325928327523872562977992836129336669323999924404349653148300196 372
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 14588028750717835858574534596482146696370333036484913931063756940971238309270 396
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 41656413344772124327488710354345801161074175442062255394430882444149905131880 396
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error 6 test runs
chip_sw_alert_handler_lpg_sleep_mode_pings 2775390456334229697551975274002280215632568224574354594719571462932602574870 372
UVM_INFO @ 2747.720178 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_entropy 21488395368927284638372441726038930858239532917317703832057938829106950177082 481
UVM_INFO @ 2638.767616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_reverse_ping_in_deep_sleep 13770921437459870993681368786736420493234237416952229207707055800748376148696 371
UVM_INFO @ 9659.043880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_pings 53340074632876241707539176934807942557685905449123227857664427714658052231429 372
UVM_INFO @ 2726.039442 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_entropy 84299587564975748647969933393985899846608400969607036892430193967931710438764 493
UVM_INFO @ 2926.350090 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_entropy 84507881003331434145895610773299233435546788320980973888711937682935560416021 493
UVM_INFO @ 2924.803044 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 6 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 66829218261630139387984051326083438205654815937889566903332832489381682522812 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 68312019868561034296664874160946178609129250192231706607915401035852489024911 None
---- STDERR ----
Another command (pid=194832) is running. Waiting for it to complete on the server (server_pid=194937)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_sleep_wake_5_bug 107244305052244528525944327214217774059522984820210048438430555310505572369036 None
---- STDERR ----
Another command (pid=208629) is running. Waiting for it to complete on the server (server_pid=194937)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 31652317906553539520582876737929920681099381991106837033491078155481687152008 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_sleep_wake_5_bug 74639394527202867658011268313538124737567216780367309261321588388588928281536 None
---- STDERR ----
Another command (pid=1144305) is running. Waiting for it to complete on the server (server_pid=194937)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 3402711061636496157904609292800949026985504918173014756896329833959151822449 None
---- STDERR ----
Another command (pid=376475) is running. Waiting for it to complete on the server (server_pid=194937)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 4 test runs
chip_sw_pwrmgr_sleep_power_glitch_reset 5938540571323161718304079079531122876655957070021427296100524179364815513146 376
UVM_ERROR @ 2441.308736 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2441.308736 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 35118835192619677066333263542234809681535792314984263255685076561719474199333 416
UVM_ERROR @ 10861.246712 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 10861.246712 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_power_glitch_reset 18326455565316858682689400991659903501883491727978983956449802425427146547293 376
UVM_ERROR @ 2769.365940 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2769.365940 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_power_glitch_reset 20064952813357878054965618992363273989126456574169672711330190058625348042751 376
UVM_ERROR @ 2734.428220 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2734.428220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:923) virtual_sequencer [chip_sw_lc_ctrl_transition_vseq] max attempt reached to get lc status LcExtClockSwitched! 4 test runs
chip_sw_lc_ctrl_transition 37905164699127351392140376749982017259912145036205120405632419944668220398869 368
UVM_INFO @ 26281.051020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_ctrl_transition 105998370779422793875366768738771103907674838779028347583266379739016073848109 410
UVM_INFO @ 38048.045228 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_ctrl_transition 55514851854463121014659638075633602198444492277592113683206548120905460986756 368
UVM_INFO @ 25784.418014 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_ctrl_transition 65490240606230703988915706625984116841517067137135323289508038201317199035324 368
UVM_INFO @ 26114.751947 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr.u_d0_spi_host*.leaf_rst_path 3 test runs
chip_sw_rstmgr_rst_cnsty_escalation 96212373366039062063800968263887204041978679116481303103790542417373906499963 364
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_rst_cnsty_escalation 64279901564762120010038463395769171125777520751504615560302345342409614092828 364
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_rst_cnsty_escalation 45956758609754620662391790120439396663880907064804198725670658177690555130746 364
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rram_rma_unlocked_vseq.sv:162) [chip_sw_rram_rma_unlocked_vseq] wait timeout occurred! 3 test runs
chip_sw_rram_rma_unlocked 49846981403292126334441709693291224578703451115907236910389000153633793379677 336
UVM_INFO @ 10010.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rram_rma_unlocked 35624676412202226218509953977263847325051529369094507535561495524517784599122 336
UVM_INFO @ 10010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rram_rma_unlocked 35519503493172337884851886388571284983678567682902934375510096279715482579023 336
UVM_INFO @ 10010.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 3 test runs
chip_sw_otp_ctrl_lc_signals_rma 63116256253042407616425554242766041032897273120823323828256116362372015542118 403
UVM_INFO @ 6118.023816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otp_ctrl_lc_signals_rma 36572241479230647931205793590459009556458565452752368996380238681713021179251 403
UVM_INFO @ 6450.514108 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otp_ctrl_lc_signals_rma 10239782560973931026275785410840970003891411670138233846218617432560675488332 403
UVM_INFO @ 6509.601445 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:340) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 3 test runs
chip_sw_hmac_multistream 113067865094451906900952908755071528668524206248404860107388090455875228442918 411
UVM_INFO @ 12010.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_hmac_multistream 8063331464966091321048806453269470626013782741860241715868943037816191050233 415
UVM_INFO @ 12010.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_hmac_multistream 54009686144710335599712570928063631055516812427364073118221678376292939457202 426
UVM_INFO @ 12010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_test_status_if.sv:65) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] SW test status must not change after reaching the pass or fail state. 3 test runs
chip_sw_clkmgr_reset_frequency 25305715209753481974458935854550940708605215317360487671705321085369446328772 399
UVM_INFO @ 7765.692280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_reset_frequency 42378926733946191171274521768608764441263108196143095855181708553047702145899 399
UVM_INFO @ 8623.861724 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_reset_frequency 93647509347279540472043138394355539351749180652822822793327603455732378587899 399
UVM_INFO @ 11740.424088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_clkmgr_jitter_frequency 50963939664217158106112128369122097565522715357464641481715479332485485295762 406
UVM_INFO @ 3110.367535 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_jitter_frequency 81024094832309757805994307097591096591240322368852760239507904407059633938560 406
UVM_INFO @ 3724.490990 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_jitter_frequency 72361038912257199517413058308181555373371481640044978193480307666452654975361 406
UVM_INFO @ 3187.138022 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_rv_dm_lc_disabled_vseq.sv:154) [chip_rv_dm_lc_disabled_vseq] Check failed rdata == exp_data (* [*] vs * [*]) RV_DM sbaddress* read back check failed, got *, expected * 3 test runs
chip_rv_dm_lc_disabled 88486860906616017123237525001546276693062723179878354959966476992423281752055 299
UVM_INFO @ 4671.360730 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_rv_dm_lc_disabled 53825767302498187021037755658715523936414374394467946643753710240603256867205 285
UVM_INFO @ 2103.177992 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_rv_dm_lc_disabled 100049080044024991943158331278469331670046029876774222090036510939163603284340 285
UVM_INFO @ 1623.868561 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 3 test runs
chip_sw_ast_clk_rst_inputs 100242373163093593585708282167689580767975634597922517513219562678620390796039 390
UVM_INFO @ 9521.900548 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_ast_clk_rst_inputs 60906740328042768407490295336332110260998877132569086961965775948125639625298 390
UVM_INFO @ 14550.102725 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_ast_clk_rst_inputs 68155249107406162170122924371545719679347490889342077329726424979095824157654 390
UVM_INFO @ 14638.642963 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 3 test runs
ate_bootstrap_flash_erase 32954966473768207626577302819748568008306608571682410083745912714245549783409 338
UVM_INFO @ 10010.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ate_bootstrap_flash_erase 54717769915003374853161074116937517150310310177781020392707430406338802812184 338
UVM_INFO @ 10010.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ate_bootstrap_flash_erase 87638225127216021856624976439935721543299581252392424271671072928477614258376 338
UVM_INFO @ 10010.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:604) [debugger] Check failed pc == exp_addr (* [*] vs * [*]) 3 test runs
rom_e2e_jtag_debug_test_unlocked0 78735286409741498914704978195191611185290817158332056446461050881946481441401 352
UVM_INFO @ 2159.939000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_jtag_debug_dev 73052860963881584150128950851212387479027898504526836934882958226123654926731 352
UVM_INFO @ 2355.214000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_jtag_debug_rma 20689271526751278708719939170246607896675494306269959593420112499292045175613 352
UVM_INFO @ 1908.147000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:614)] CHECK-fail: Unexpected mtval: expected *, got * 3 test runs
chip_sw_all_escalation_resets 108337699326223054517873859785862328763315840949438271918070206370618071280817 382
UVM_INFO @ 2461.985752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 71744198334224831127236300967308781445093602084287110046770903247991811138843 382
UVM_INFO @ 3089.062192 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 62275407516572810122208638207591887306388939218290483984021252432593358581530 382
UVM_INFO @ 2872.889614 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal triggered unexpectedly 3 test runs
chip_sw_all_escalation_resets 79875480830984718452331595163314819061229413956865396357468937672317972078276 381
UVM_INFO @ 2968.851468 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 113155359089261295993420905789704417139373494171830647791248460228275011336125 381
UVM_INFO @ 2939.216504 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 103689761735444690948687549623177940178135094393514478609725600835376990153310 381
UVM_INFO @ 3078.716648 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_riscv_driver.sv:208) driver [driver] Could not activate RV_DM after * attempts! 2 test runs
chip_jtag_mem_access 27417654345686052482104361129101401347112685655336681056449661611200922795888 5364
UVM_INFO @ 2675.349560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_jtag_mem_access 57153334729737306476649534065101190395204540970447098834111247144875147578763 5364
UVM_INFO @ 2608.121427 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:887) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl 2 test runs
rom_raw_unlock 78707062661782101778652598648799515560086459273084287960625039844046323009815 377
UVM_INFO @ 10795.114639 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_raw_unlock 16236532851762197495115857426470336780332806531562423588976202792512307870636 377
UVM_INFO @ 8191.578596 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 2 test runs
chip_sw_spi_device_pass_through_collision 21106912909673806416410586446756701645128559981033720084160283192207212700333 390
UVM_INFO @ 3086.696970 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pass_through_collision 19516881764070171105738909989249470812455559306174033510251928732528464040373 390
UVM_INFO @ 2875.972799 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch 1 test run
chip_sw_spi_device_pass_through_collision 45432675142232644339237005753291036855269993394266536610693207266300333122010 392
host_rsp:
-------------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------------
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:715)] CHECK-fail: Alert handler NMI state not expected: 1 test run
chip_sw_otp_ctrl_escalation 25973505560518439304785427087171780684519463934864708559963121335634411169552 378
alert_enable:1
alert_raised:0
UVM_INFO @ 3685.363058 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:887) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl 1 test run
chip_sw_lc_ctrl_raw_to_scrap 67031620453977679757601593335924796417965765744742403675059184789257790144513 374
UVM_INFO @ 9099.122727 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:370)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 86316072749437289302238742532917033513897225735419508916149885381389859408682 370
UVM_INFO @ 2855.249702 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:923) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_ctrl_rand_to_scrap 27006315265905696210192774120522848211268821789190509802698099611082107314447 365
UVM_INFO @ 26175.114952 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:923) virtual_sequencer [chip_sw_lc_volatile_raw_unlock_vseq] max attempt reached to get lc status LcTokenError! 1 test run
chip_sw_lc_ctrl_volatile_raw_unlock 86441860922697921491472491265490403066884469990322869936157344547599798637581 371
UVM_INFO @ 26219.845362 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(buf_intg_err == '0)' 1 test run
chip_sw_sysrst_ctrl_outputs 31426626826942932465028514636950194524505279166716667428336357575495059807292 408
UVM_ERROR @ 3782.334994 us: (rram_phy_rd.sv:697) [ASSERT FAILED] IntgError
UVM_INFO @ 3782.334994 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:445)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 88916390356321383612702225648239052189314693030384749804886199470530692340301 370
UVM_INFO @ 3021.530130 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:923) virtual_sequencer [chip_sw_lc_volatile_raw_unlock_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 68550740454841431887721999783636076813777320315381481874838254928572080260171 377
UVM_INFO @ 25769.138084 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:340)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 70191623890003309311946735388881502882020566820610435197741069059915282663748 370
UVM_INFO @ 2897.259542 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rv_jtag_o == '0)' 1 test run
chip_sw_rv_dm_access_after_escalation_reset 34735464534166278941705783870420325696864190682438617086493266480743989806625 380
UVM_ERROR @ 3212.480072 us: (pinmux_strap_sampling.sv:516) [ASSERT FAILED] RvTapOff1_A
UVM_INFO @ 3212.480072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:1004) [chip_sw_lc_volatile_raw_unlock_vseq] Check failed (!(transition_ctrl & (* << *))) VOLATILE_RAW_UNLOCK is not expected to be supported by this top-level. Check the SecVolatileRawUnlockEn parameter configuration. 1 test run
rom_volatile_raw_unlock 73138994457544398933594696314032324942243247968473759841351664731589295847866 363
UVM_INFO @ 2394.673676 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: chip_reg_block.rram_ctrl_core.region_cfg_regwen_* reset value: * 1 test run
chip_csr_mem_rw_with_rand_reset 36965546948923364953230639259842548684430316950364284090527197830710692774252 310
UVM_INFO @ 7769.337224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_if.sv:154) [tb.dut.chip_if] Detected an X on MioPadIor* (num=39) 1 test run
chip_padctrl_attributes 46636084051359852750003981493278715120741856674900375887794109053236275514348 344
UVM_INFO @ 1525.641657 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---