Simulation Results: sysrst_ctrl

 
22/08/2026 09:08:29 DVSim: v1.49.0 sha: 34ceb5e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.71 %
  • code
  • 98.63 %
  • assert
  • 98.95 %
  • func
  • 86.55 %
  • line
  • 99.46 %
  • branch
  • 99.52 %
  • cond
  • 98.01 %
  • toggle
  • 100.00 %
  • FSM
  • 96.15 %
Validation stages
V1
100.00%
V2
97.90%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
sysrst_ctrl_smoke 7.880s 2111.885us 10 10 100.00
input_output_inverted 10 10 100.00
sysrst_ctrl_in_out_inverted 8.990s 2452.515us 10 10 100.00
combo_detect_ec_rst 5 5 100.00
sysrst_ctrl_combo_detect_ec_rst 8.670s 2389.518us 5 5 100.00
combo_detect_ec_rst_with_pre_cond 5 5 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 8.440s 2343.263us 5 5 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 4.050s 6154.816us 1 1 100.00
csr_rw 5 5 100.00
sysrst_ctrl_csr_rw 7.800s 2037.204us 5 5 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 105.680s 68130.167us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 4.030s 2614.777us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 4.440s 2080.152us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sysrst_ctrl_csr_rw 7.800s 2037.204us 5 5 100.00
sysrst_ctrl_csr_aliasing 4.030s 2614.777us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 25 25 100.00
sysrst_ctrl_combo_detect 490.710s 172645.530us 25 25 100.00
combo_detect_with_pre_cond 94 100 94.00
sysrst_ctrl_combo_detect_with_pre_cond 567.070s 200584.268us 94 100 94.00
auto_block_key_outputs 25 25 100.00
sysrst_ctrl_auto_blk_key_output 736.310s 240098.731us 25 25 100.00
keyboard_input_triggered_interrupt 50 50 100.00
sysrst_ctrl_edge_detect 1535.020s 777770.794us 50 50 100.00
pin_output_keyboard_inversion_control 10 10 100.00
sysrst_ctrl_pin_override_test 8.660s 2510.530us 10 10 100.00
pin_input_value_accessibility 10 10 100.00
sysrst_ctrl_pin_access_test 5.680s 2113.941us 10 10 100.00
ec_power_on_reset 10 10 100.00
sysrst_ctrl_ec_pwr_on_rst 12.410s 5573.205us 10 10 100.00
flash_write_protect_output 10 10 100.00
sysrst_ctrl_flash_wr_prot_out 9.020s 2611.699us 10 10 100.00
ultra_low_power_test 24 25 96.00
sysrst_ctrl_ultra_low_pwr 930.860s 2451479.464us 24 25 96.00
sysrst_ctrl_feature_disable 2 2 100.00
sysrst_ctrl_feature_disable 51.480s 35304.359us 2 2 100.00
stress_all 10 10 100.00
sysrst_ctrl_stress_all 811.010s 316066.042us 10 10 100.00
alert_test 10 10 100.00
sysrst_ctrl_alert_test 7.490s 2012.573us 10 10 100.00
intr_test 10 10 100.00
sysrst_ctrl_intr_test 7.830s 2016.676us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sysrst_ctrl_tl_errors 8.830s 2095.073us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sysrst_ctrl_tl_errors 8.830s 2095.073us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sysrst_ctrl_csr_hw_reset 4.050s 6154.816us 1 1 100.00
sysrst_ctrl_csr_rw 7.800s 2037.204us 5 5 100.00
sysrst_ctrl_csr_aliasing 4.030s 2614.777us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 29.050s 10201.438us 5 5 100.00
tl_d_partial_access 12 12 100.00
sysrst_ctrl_csr_hw_reset 4.050s 6154.816us 1 1 100.00
sysrst_ctrl_csr_rw 7.800s 2037.204us 5 5 100.00
sysrst_ctrl_csr_aliasing 4.030s 2614.777us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 29.050s 10201.438us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
sysrst_ctrl_sec_cm 76.480s 42031.374us 5 5 100.00
sysrst_ctrl_tl_intg_err 145.660s 42411.872us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
sysrst_ctrl_tl_intg_err 145.660s 42411.872us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
sysrst_ctrl_stress_all_with_rand_reset 17.780s 5566.863us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) 3 test runs
sysrst_ctrl_combo_detect_with_pre_cond 109890452597600366332379756746685366476961315453333198611182304413754988167671 681
UVM_INFO @ 35217987768 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x32
UVM_INFO @ 35218017768 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x1a
UVM_INFO @ 36197477768 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2
UVM_INFO @ 36212360334 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= 1d
sysrst_ctrl_combo_detect_with_pre_cond 107866974772148723049309746019105560324288183262413577434929876141996721846959 689
UVM_ERROR @ 61301776295 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 61301776295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_combo_detect_with_pre_cond 68775085117043917245544803856279586743022834779301798937653087536453901448031 682
UVM_INFO @ 25378060154 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 25398060154 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 35602666885 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2d
UVM_INFO @ 35602809741 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x14
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*]) 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 93816749827055494157055692822463676895558410636221455677151003251237108652655 672
UVM_INFO @ 13572741935 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 13592741935 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_ERROR @ 13617763070 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 4 [0x4])
UVM_INFO @ 13617763070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)  1 test run
sysrst_ctrl_ultra_low_pwr 19213815872363748569421390982816028721409521520932152424066001879582086128701 661
UVM_INFO @ 2263204523 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
UVM_INFO @ 451493204523 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
UVM_INFO @ 750808204523 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 750857098177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(2) +/-* 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 70549130989144228703681665503993648172959384791904242951799176469972759762827 697
UVM_ERROR @ 63888041057 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(2) +/-4
UVM_INFO @ 63888041057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(9) vs exp(5) +/-* 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 53566656191988263385592430529580151821009600346046128037491492063549879670515 673
UVM_ERROR @ 13430623910 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(9) vs exp(5) +/-4
UVM_INFO @ 13430623910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---