Simulation Results: sysrst_ctrl

 
29/08/2026 03:59:48 DVSim: v1.49.0 sha: 0098135 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.53 %
  • code
  • 97.99 %
  • assert
  • 98.58 %
  • func
  • 84.03 %
  • line
  • 99.24 %
  • branch
  • 99.22 %
  • cond
  • 97.88 %
  • toggle
  • 100.00 %
  • FSM
  • 93.59 %
Validation stages
V1
100.00%
V2
97.90%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
sysrst_ctrl_smoke 6.950s 2108.944us 10 10 100.00
input_output_inverted 10 10 100.00
sysrst_ctrl_in_out_inverted 8.530s 2483.189us 10 10 100.00
combo_detect_ec_rst 5 5 100.00
sysrst_ctrl_combo_detect_ec_rst 5.540s 2247.439us 5 5 100.00
combo_detect_ec_rst_with_pre_cond 5 5 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 8.150s 2299.913us 5 5 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 18.720s 6049.801us 1 1 100.00
csr_rw 5 5 100.00
sysrst_ctrl_csr_rw 5.350s 2030.144us 5 5 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 49.460s 51448.648us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 2.690s 2146.526us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 6.900s 2041.583us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sysrst_ctrl_csr_rw 5.350s 2030.144us 5 5 100.00
sysrst_ctrl_csr_aliasing 2.690s 2146.526us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 25 25 100.00
sysrst_ctrl_combo_detect 424.240s 183760.844us 25 25 100.00
combo_detect_with_pre_cond 94 100 94.00
sysrst_ctrl_combo_detect_with_pre_cond 331.710s 149127.037us 94 100 94.00
auto_block_key_outputs 25 25 100.00
sysrst_ctrl_auto_blk_key_output 247.670s 158699.476us 25 25 100.00
keyboard_input_triggered_interrupt 50 50 100.00
sysrst_ctrl_edge_detect 2112.410s 1696610.990us 50 50 100.00
pin_output_keyboard_inversion_control 10 10 100.00
sysrst_ctrl_pin_override_test 6.890s 2509.889us 10 10 100.00
pin_input_value_accessibility 10 10 100.00
sysrst_ctrl_pin_access_test 7.260s 2232.495us 10 10 100.00
ec_power_on_reset 10 10 100.00
sysrst_ctrl_ec_pwr_on_rst 2201.350s 980288.366us 10 10 100.00
flash_write_protect_output 10 10 100.00
sysrst_ctrl_flash_wr_prot_out 9.610s 2613.007us 10 10 100.00
ultra_low_power_test 25 25 100.00
sysrst_ctrl_ultra_low_pwr 318.690s 1603951.152us 25 25 100.00
sysrst_ctrl_feature_disable 2 2 100.00
sysrst_ctrl_feature_disable 30.950s 37137.134us 2 2 100.00
stress_all 9 10 90.00
sysrst_ctrl_stress_all 876.330s 2100155.830us 9 10 90.00
alert_test 10 10 100.00
sysrst_ctrl_alert_test 6.530s 2011.766us 10 10 100.00
intr_test 10 10 100.00
sysrst_ctrl_intr_test 7.200s 2019.539us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sysrst_ctrl_tl_errors 8.290s 2063.781us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sysrst_ctrl_tl_errors 8.290s 2063.781us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sysrst_ctrl_csr_hw_reset 18.720s 6049.801us 1 1 100.00
sysrst_ctrl_csr_rw 5.350s 2030.144us 5 5 100.00
sysrst_ctrl_csr_aliasing 2.690s 2146.526us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 21.980s 9276.037us 5 5 100.00
tl_d_partial_access 12 12 100.00
sysrst_ctrl_csr_hw_reset 18.720s 6049.801us 1 1 100.00
sysrst_ctrl_csr_rw 5.350s 2030.144us 5 5 100.00
sysrst_ctrl_csr_aliasing 2.690s 2146.526us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 21.980s 9276.037us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
sysrst_ctrl_sec_cm 56.400s 22010.930us 5 5 100.00
sysrst_ctrl_tl_intg_err 111.120s 42469.841us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
sysrst_ctrl_tl_intg_err 111.120s 42469.841us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 9 10 90.00
sysrst_ctrl_stress_all_with_rand_reset 22.940s 324828.368us 9 10 90.00

Error Messages

   Test seed line log context
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(6) vs exp(2) +/-* 2 test runs
sysrst_ctrl_combo_detect_with_pre_cond 100274293148239450274624936491780352599095215100223639979728421667793408848085 691
UVM_INFO @ 61659008486 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2c
UVM_INFO @ 61659133487 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x27
UVM_INFO @ 62036412657 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0
UVM_INFO @ 62051412657 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= 1e
sysrst_ctrl_combo_detect_with_pre_cond 92869893255548071455091879685111867589130617559313967684168764290537491802736 732
UVM_ERROR @ 76242803442 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(6) vs exp(2) +/-4
UVM_INFO @ 76242803442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)  1 test run
sysrst_ctrl_stress_all 89611053897395236165594449154701288074393309388233260379269398900542264382350 667
UVM_INFO @ 4175342598 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
UVM_INFO @ 5590342598 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 5596164649 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_flash_wr_prot_vseq
UVM_INFO @ 7595384649 ps: (sysrst_ctrl_flash_wr_prot_vseq.sv:23) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_flash_wr_prot_vseq] Starting the body from flash_wr_prot_vseq
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 107435292131126946179939522683804984903958381912575917427097073124730004720724 677
UVM_ERROR @ 24879517231 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 24879517231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:103) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (* [*] vs * [*]) 1 test run
sysrst_ctrl_stress_all_with_rand_reset 44108768471261564729432672656640391644014836795651113285486326776625411193600 666
UVM_ERROR @ 4323952870 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:115) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (0 [0x0] vs 1 [0x1])
UVM_INFO @ 4323952870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 82238396997111224746906163738347208940706161048076390149896450698209266245168 714
UVM_ERROR @ 54150029242 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 54150029242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*]) 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 35152157957072473423670938137331946782009962368021610990983265378460726625977 680
UVM_ERROR @ 27026587401 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 4 [0x4])
UVM_INFO @ 27026587401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(8) vs exp(3) +/-* 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 48602420040868464563443895002854484572732456752512140895197106194568007957549 675
UVM_INFO @ 12647795054 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 12667795054 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 22818448172 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x18
UVM_INFO @ 22818479423 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x11