Simulation Results: chip

 
05/09/2026 08:56:33 DVSim: v1.49.0 sha: 1e1dace json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.97 %
  • code
  • 77.26 %
  • assert
  • 97.34 %
  • func
  • 98.32 %
  • line
  • 94.04 %
  • branch
  • 94.30 %
  • cond
  • 92.71 %
  • toggle
  • 71.91 %
  • FSM
  • 33.33 %
Validation stages
V1
97.60%
V2
87.23%
V2S
100.00%
V3
79.49%
unmapped
13.64%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 9 9 100.00
chip_sw_example_rom 181.060s 2116.815us 3 3 100.00
chip_sw_example_manufacturer 350.990s 2909.201us 3 3 100.00
chip_sw_example_concurrency 309.660s 2633.367us 3 3 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 607.950s 8754.192us 1 1 100.00
csr_rw 5 5 100.00
chip_csr_rw 1410.600s 11591.425us 5 5 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 1685.590s 12428.024us 1 1 100.00
csr_aliasing 0 1 0.00
chip_csr_aliasing 10800.190s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 3 5 60.00
chip_csr_mem_rw_with_rand_reset 1448.090s 15328.763us 3 5 60.00
regwen_csr_and_corresponding_lockable_csr 5 6 83.33
chip_csr_aliasing 10800.190s 0.000us 0 1 0.00
chip_csr_rw 1410.600s 11591.425us 5 5 100.00
xbar_smoke 50 50 100.00
xbar_smoke 13.710s 249.976us 50 50 100.00
chip_sw_gpio_out 3 3 100.00
chip_sw_gpio 595.530s 3863.981us 3 3 100.00
chip_sw_gpio_in 3 3 100.00
chip_sw_gpio 595.530s 3863.981us 3 3 100.00
chip_sw_gpio_irq 3 3 100.00
chip_sw_gpio 595.530s 3863.981us 3 3 100.00
chip_sw_uart_tx_rx 5 5 100.00
chip_sw_uart_tx_rx 797.130s 4615.560us 5 5 100.00
chip_sw_uart_rx_overflow 20 20 100.00
chip_sw_uart_tx_rx 797.130s 4615.560us 5 5 100.00
chip_sw_uart_tx_rx_idx1 784.590s 4386.731us 5 5 100.00
chip_sw_uart_tx_rx_idx2 802.640s 4366.696us 5 5 100.00
chip_sw_uart_tx_rx_idx3 747.830s 4531.505us 5 5 100.00
chip_sw_uart_baud_rate 20 20 100.00
chip_sw_uart_rand_baudrate 3273.400s 13312.138us 20 20 100.00
chip_sw_uart_tx_rx_alt_clk_freq 10 10 100.00
chip_sw_uart_tx_rx_alt_clk_freq 3184.490s 13047.564us 5 5 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 2208.010s 12870.819us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 10 10 100.00
chip_padctrl_attributes 873.020s 11578.677us 10 10 100.00
chip_padctrl_attributes 10 10 100.00
chip_padctrl_attributes 873.020s 11578.677us 10 10 100.00
chip_sw_sleep_pin_mio_dio_val 3 3 100.00
chip_sw_sleep_pin_mio_dio_val 470.240s 3061.205us 3 3 100.00
chip_sw_sleep_pin_wake 0 3 0.00
chip_sw_sleep_pin_wake 337.830s 2705.709us 0 3 0.00
chip_sw_sleep_pin_retention 0 3 0.00
chip_sw_sleep_pin_retention 337.210s 3340.094us 0 3 0.00
chip_sw_tap_strap_sampling 20 20 100.00
chip_tap_straps_dev 1506.240s 11389.209us 5 5 100.00
chip_tap_straps_testunlock0 1017.940s 8238.516us 5 5 100.00
chip_tap_straps_rma 1082.900s 8526.942us 5 5 100.00
chip_tap_straps_prod 2055.980s 18362.369us 5 5 100.00
chip_sw_data_integrity 6 6 100.00
chip_sw_data_integrity_escalation 946.050s 5277.057us 6 6 100.00
chip_sw_instruction_integrity 6 6 100.00
chip_sw_data_integrity_escalation 946.050s 5277.057us 6 6 100.00
chip_sw_ast_clk_outputs 3 3 100.00
chip_sw_ast_clk_outputs 1238.190s 7574.552us 3 3 100.00
chip_sw_ast_clk_rst_inputs 0 3 0.00
chip_sw_ast_clk_rst_inputs 2810.590s 12919.607us 0 3 0.00
chip_sw_ast_sys_clk_jitter 24 24 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 6057.610s 18989.478us 3 3 100.00
chip_sw_aes_enc_jitter_en 444.840s 3202.532us 3 3 100.00
chip_sw_edn_entropy_reqs_jitter 1436.080s 6620.096us 3 3 100.00
chip_sw_hmac_enc_jitter_en 358.940s 2767.628us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 3126.670s 11545.422us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 426.280s 3059.281us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 667.570s 4003.597us 3 3 100.00
chip_sw_clkmgr_jitter 368.670s 2686.013us 3 3 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 334.060s 2636.774us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 5 8 62.50
chip_sw_sensor_ctrl_alert 1216.270s 6722.508us 5 5 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 272.170s 2685.273us 0 3 0.00
chip_sw_sensor_ctrl_ast_status 3 3 100.00
chip_sw_sensor_ctrl_status 348.050s 2456.953us 3 3 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 0 3 0.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 272.170s 2685.273us 0 3 0.00
chip_sw_smoketest 48 48 100.00
chip_sw_aes_smoketest 390.450s 3153.791us 3 3 100.00
chip_sw_aon_timer_smoketest 439.130s 3602.450us 3 3 100.00
chip_sw_clkmgr_smoketest 324.910s 3083.879us 3 3 100.00
chip_sw_csrng_smoketest 379.080s 3260.344us 3 3 100.00
chip_sw_entropy_src_smoketest 1724.640s 6879.382us 3 3 100.00
chip_sw_gpio_smoketest 386.710s 3130.081us 3 3 100.00
chip_sw_hmac_smoketest 502.260s 3506.985us 3 3 100.00
chip_sw_kmac_smoketest 434.820s 3244.585us 3 3 100.00
chip_sw_otbn_smoketest 3176.450s 10757.530us 3 3 100.00
chip_sw_pwrmgr_smoketest 683.760s 6368.597us 3 3 100.00
chip_sw_pwrmgr_usbdev_smoketest 690.820s 5567.008us 3 3 100.00
chip_sw_rv_plic_smoketest 277.210s 3139.793us 3 3 100.00
chip_sw_rv_timer_smoketest 400.440s 3487.188us 3 3 100.00
chip_sw_rstmgr_smoketest 375.710s 2671.576us 3 3 100.00
chip_sw_sram_ctrl_smoketest 411.270s 2978.743us 3 3 100.00
chip_sw_uart_smoketest 465.820s 3049.577us 3 3 100.00
chip_sw_otp_smoketest 3 3 100.00
chip_sw_otp_ctrl_smoketest 353.800s 3407.750us 3 3 100.00
chip_sw_rom_functests 3 3 100.00
rom_keymgr_dpe_functest 729.900s 3856.301us 3 3 100.00
chip_sw_boot 0 3 0.00
chip_sw_uart_tx_rx_bootstrap 28800.196s 0.000us 0 3 0.00
chip_sw_secure_boot 3 3 100.00
rom_e2e_smoke 5319.610s 14991.660us 3 3 100.00
chip_sw_rom_raw_unlock 2 3 66.67
rom_raw_unlock 2002.600s 22052.128us 2 3 66.67
chip_sw_power_idle_load 3 3 100.00
chip_sw_power_idle_load 779.510s 4124.640us 3 3 100.00
chip_sw_power_sleep_load 1 3 33.33
chip_sw_power_sleep_load 772.900s 10154.174us 1 3 33.33
chip_sw_exit_test_unlocked_bootstrap 0 3 0.00
chip_sw_exit_test_unlocked_bootstrap 13200.203s 0.000us 0 3 0.00
tl_d_oob_addr_access 22 30 73.33
chip_tl_errors 3600.203s 0.000us 22 30 73.33
tl_d_illegal_access 22 30 73.33
chip_tl_errors 3600.203s 0.000us 22 30 73.33
tl_d_outstanding_access 9 12 75.00
chip_csr_aliasing 10800.190s 0.000us 0 1 0.00
chip_same_csr_outstanding 4879.790s 28744.735us 3 5 60.00
chip_csr_hw_reset 607.950s 8754.192us 1 1 100.00
chip_csr_rw 1410.600s 11591.425us 5 5 100.00
tl_d_partial_access 9 12 75.00
chip_csr_aliasing 10800.190s 0.000us 0 1 0.00
chip_same_csr_outstanding 4879.790s 28744.735us 3 5 60.00
chip_csr_hw_reset 607.950s 8754.192us 1 1 100.00
chip_csr_rw 1410.600s 11591.425us 5 5 100.00
xbar_base_random_sequence 50 50 100.00
xbar_random 97.940s 2103.651us 50 50 100.00
xbar_random_delay 300 300 100.00
xbar_smoke_zero_delays 8.110s 42.460us 50 50 100.00
xbar_smoke_large_delays 111.560s 9862.502us 50 50 100.00
xbar_smoke_slow_rsp 110.800s 5831.210us 50 50 100.00
xbar_random_zero_delays 51.070s 510.366us 50 50 100.00
xbar_random_large_delays 547.720s 49940.508us 50 50 100.00
xbar_random_slow_rsp 533.440s 29529.459us 50 50 100.00
xbar_unmapped_address 100 100 100.00
xbar_unmapped_addr 63.980s 1270.000us 50 50 100.00
xbar_error_and_unmapped_addr 60.610s 1446.002us 50 50 100.00
xbar_error_cases 100 100 100.00
xbar_error_random 91.660s 2015.254us 50 50 100.00
xbar_error_and_unmapped_addr 60.610s 1446.002us 50 50 100.00
xbar_all_access_same_device 100 100 100.00
xbar_access_same_device 167.720s 3244.978us 50 50 100.00
xbar_access_same_device_slow_rsp 1258.010s 83505.334us 50 50 100.00
xbar_all_hosts_use_same_source_id 50 50 100.00
xbar_same_source 97.080s 2507.603us 50 50 100.00
xbar_stress_all 100 100 100.00
xbar_stress_all 953.860s 19963.946us 50 50 100.00
xbar_stress_all_with_error 619.440s 14452.790us 50 50 100.00
xbar_stress_with_reset 100 100 100.00
xbar_stress_all_with_rand_reset 1009.340s 10058.133us 50 50 100.00
xbar_stress_all_with_reset_error 874.320s 16331.832us 50 50 100.00
rom_e2e_smoke 3 3 100.00
rom_e2e_smoke 5319.610s 14991.660us 3 3 100.00
rom_e2e_shutdown_output 3 3 100.00
rom_e2e_shutdown_output 5497.780s 42532.975us 3 3 100.00
rom_e2e_shutdown_exception_c 3 3 100.00
rom_e2e_shutdown_exception_c 7151.980s 38841.077us 3 3 100.00
rom_e2e_boot_policy_valid 15 15 100.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 4020.390s 10828.346us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 5779.560s 15892.684us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 5519.240s 15390.937us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 5902.340s 16482.948us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 5518.890s 15494.435us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 4058.780s 10999.764us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 5841.350s 15755.732us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 5661.340s 15458.651us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 5693.330s 15751.385us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 5520.470s 14996.816us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 7335.710s 17694.736us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 9853.570s 24130.550us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 9486.610s 24293.603us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 9841.990s 24721.352us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 9331.630s 23158.136us 1 1 100.00
rom_e2e_sigverify_always 15 15 100.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 7627.720s 22290.993us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 9289.870s 23121.703us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 10535.170s 36475.565us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 8823.030s 23520.000us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 9131.120s 29177.220us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 5136.620s 25460.779us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 6137.650s 30412.914us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 6009.050s 28585.649us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 5128.670s 18894.423us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 5193.690s 17434.280us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 4402.600s 19035.974us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 5208.950s 14244.695us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 5165.790s 13873.692us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 5296.960s 18511.702us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 4827.540s 13442.422us 1 1 100.00
rom_e2e_asm_init 15 15 100.00
rom_e2e_asm_init_test_unlocked0 4292.800s 12170.170us 3 3 100.00
rom_e2e_asm_init_dev 5936.880s 17020.054us 3 3 100.00
rom_e2e_asm_init_prod 5791.700s 16300.195us 3 3 100.00
rom_e2e_asm_init_prod_end 5958.070s 16166.688us 3 3 100.00
rom_e2e_asm_init_rma 5628.880s 15250.640us 3 3 100.00
rom_e2e_keymgr_dpe_init 9 9 100.00
rom_e2e_keymgr_dpe_init_rom_ext_meas 10887.330s 29428.850us 3 3 100.00
rom_e2e_keymgr_dpe_init_rom_ext_no_meas 11219.920s 30129.575us 3 3 100.00
rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas 10838.990s 31092.892us 3 3 100.00
rom_e2e_static_critical 3 3 100.00
rom_e2e_static_critical 5790.880s 16771.975us 3 3 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.200s 0.000us 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.200s 0.000us 0 3 0.00
chip_sw_aes_enc 6 6 100.00
chip_sw_aes_enc 347.150s 2673.859us 3 3 100.00
chip_sw_aes_enc_jitter_en 444.840s 3202.532us 3 3 100.00
chip_sw_aes_entropy 3 3 100.00
chip_sw_aes_entropy 328.180s 2568.125us 3 3 100.00
chip_sw_aes_idle 3 3 100.00
chip_sw_aes_idle 349.820s 2903.305us 3 3 100.00
chip_sw_aes_sideload 3 3 100.00
chip_sw_keymgr_dpe_sideload_aes 2550.850s 9732.125us 3 3 100.00
chip_sw_alert_handler_alerts 0 3 0.00
chip_sw_alert_test 438.020s 3165.207us 0 3 0.00
chip_sw_alert_handler_escalations 3 3 100.00
chip_sw_alert_handler_escalation 736.980s 4781.074us 3 3 100.00
chip_sw_all_escalation_resets 89 100 89.00
chip_sw_all_escalation_resets 945.540s 5848.553us 89 100 89.00
chip_sw_alert_handler_irqs 9 9 100.00
chip_plic_all_irqs_0 948.040s 5228.670us 3 3 100.00
chip_plic_all_irqs_10 610.430s 4118.808us 3 3 100.00
chip_plic_all_irqs_20 627.580s 4071.337us 3 3 100.00
chip_sw_alert_handler_entropy 0 3 0.00
chip_sw_alert_handler_entropy 394.420s 3177.551us 0 3 0.00
chip_sw_alert_handler_crashdump 3 3 100.00
chip_sw_rstmgr_alert_info 1926.210s 12093.606us 3 3 100.00
chip_sw_alert_handler_ping_timeout 3 3 100.00
chip_sw_alert_handler_ping_timeout 1149.130s 7953.565us 3 3 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 90 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 415.620s 2896.596us 0 90 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 3 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 425.020s 2993.263us 0 3 0.00
chip_sw_alert_handler_lpg_clock_off 3 3 100.00
chip_sw_alert_handler_lpg_clkoff 2276.080s 8474.674us 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 2013.950s 8153.050us 3 3 100.00
chip_sw_alert_handler_ping_ok 3 3 100.00
chip_sw_alert_handler_ping_ok 1666.170s 7524.969us 3 3 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 0 3 0.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 14400.212s 0.000us 0 3 0.00
chip_sw_aon_timer_wakeup_irq 3 3 100.00
chip_sw_aon_timer_irq 568.340s 4556.634us 3 3 100.00
chip_sw_aon_timer_sleep_wakeup 3 3 100.00
chip_sw_pwrmgr_smoketest 683.760s 6368.597us 3 3 100.00
chip_sw_aon_timer_wdog_bark_irq 3 3 100.00
chip_sw_aon_timer_irq 568.340s 4556.634us 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 1030.570s 7741.934us 3 3 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 1030.570s 7741.934us 3 3 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 5 5 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 710.480s 7334.924us 5 5 100.00
chip_sw_aon_timer_wdog_lc_escalate 3 3 100.00
chip_sw_aon_timer_wdog_lc_escalate 802.080s 5051.160us 3 3 100.00
chip_sw_clkmgr_idle_trans 12 12 100.00
chip_sw_otbn_randomness 1248.800s 5707.156us 3 3 100.00
chip_sw_aes_idle 349.820s 2903.305us 3 3 100.00
chip_sw_hmac_enc_idle 406.080s 3146.419us 3 3 100.00
chip_sw_kmac_idle 414.090s 3358.460us 3 3 100.00
chip_sw_clkmgr_off_trans 12 12 100.00
chip_sw_clkmgr_off_aes_trans 550.290s 4324.072us 3 3 100.00
chip_sw_clkmgr_off_hmac_trans 560.690s 3706.606us 3 3 100.00
chip_sw_clkmgr_off_kmac_trans 704.030s 4474.023us 3 3 100.00
chip_sw_clkmgr_off_otbn_trans 520.200s 4376.732us 3 3 100.00
chip_sw_clkmgr_off_peri 3 3 100.00
chip_sw_clkmgr_off_peri 1515.080s 9637.886us 3 3 100.00
chip_sw_clkmgr_div 21 21 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 845.660s 4098.872us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 763.110s 4286.842us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 821.590s 4568.252us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 815.020s 5271.877us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 802.350s 3735.779us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 753.110s 4651.759us 3 3 100.00
chip_sw_ast_clk_outputs 1238.190s 7574.552us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 2776.760s 23809.062us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw 6 6 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 821.590s 4568.252us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 815.020s 5271.877us 3 3 100.00
chip_sw_clkmgr_jitter 24 24 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 6057.610s 18989.478us 3 3 100.00
chip_sw_aes_enc_jitter_en 444.840s 3202.532us 3 3 100.00
chip_sw_edn_entropy_reqs_jitter 1436.080s 6620.096us 3 3 100.00
chip_sw_hmac_enc_jitter_en 358.940s 2767.628us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 3126.670s 11545.422us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 426.280s 3059.281us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 667.570s 4003.597us 3 3 100.00
chip_sw_clkmgr_jitter 368.670s 2686.013us 3 3 100.00
chip_sw_clkmgr_extended_range 24 24 100.00
chip_sw_clkmgr_jitter_reduced_freq 346.680s 3006.598us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 6494.060s 25652.192us 3 3 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 350.980s 3392.613us 3 3 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 320.040s 3189.478us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq 2614.490s 14101.729us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 400.040s 3344.897us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 772.700s 5116.725us 3 3 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 6593.840s 27564.581us 3 3 100.00
chip_sw_clkmgr_deep_sleep_frequency 3 3 100.00
chip_sw_ast_clk_outputs 1238.190s 7574.552us 3 3 100.00
chip_sw_clkmgr_sleep_frequency 0 3 0.00
chip_sw_clkmgr_sleep_frequency 760.780s 4760.358us 0 3 0.00
chip_sw_clkmgr_reset_frequency 0 3 0.00
chip_sw_clkmgr_reset_frequency 1055.210s 8489.889us 0 3 0.00
chip_sw_clkmgr_escalation_reset 89 100 89.00
chip_sw_all_escalation_resets 945.540s 5848.553us 89 100 89.00
chip_sw_clkmgr_alert_handler_clock_enables 3 3 100.00
chip_sw_alert_handler_lpg_clkoff 2276.080s 8474.674us 3 3 100.00
chip_sw_csrng_edn_cmd 3 3 100.00
chip_sw_entropy_src_csrng 4036.180s 24619.940us 3 3 100.00
chip_sw_csrng_fuse_en_sw_app_read 3 3 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 669.470s 3473.046us 3 3 100.00
chip_sw_csrng_lc_hw_debug_en 3 3 100.00
chip_sw_csrng_lc_hw_debug_en_test 1531.330s 9924.636us 3 3 100.00
chip_sw_csrng_known_answer_tests 3 3 100.00
chip_sw_csrng_kat_test 454.310s 3251.656us 3 3 100.00
chip_sw_edn_entropy_reqs 16 16 100.00
chip_sw_csrng_edn_concurrency 10569.590s 32403.467us 10 10 100.00
chip_sw_entropy_src_ast_rng_req 369.360s 2946.760us 3 3 100.00
chip_sw_edn_entropy_reqs 1513.040s 6201.127us 3 3 100.00
chip_sw_entropy_src_ast_rng_req 3 3 100.00
chip_sw_entropy_src_ast_rng_req 369.360s 2946.760us 3 3 100.00
chip_sw_entropy_src_csrng 3 3 100.00
chip_sw_entropy_src_csrng 4036.180s 24619.940us 3 3 100.00
chip_sw_entropy_src_known_answer_tests 3 3 100.00
chip_sw_entropy_src_kat_test 383.270s 3182.655us 3 3 100.00
chip_sw_hmac_enc 6 6 100.00
chip_sw_hmac_enc 437.180s 2689.117us 3 3 100.00
chip_sw_hmac_enc_jitter_en 358.940s 2767.628us 3 3 100.00
chip_sw_hmac_idle 3 3 100.00
chip_sw_hmac_enc_idle 406.080s 3146.419us 3 3 100.00
chip_sw_hmac_all_configurations 3 3 100.00
chip_sw_hmac_oneshot 2664.050s 10422.941us 3 3 100.00
chip_sw_hmac_multistream_mode 0 3 0.00
chip_sw_hmac_multistream 3600.193s 0.000us 0 3 0.00
chip_sw_i2c_host_tx_rx 9 9 100.00
chip_sw_i2c_host_tx_rx 816.610s 4681.767us 3 3 100.00
chip_sw_i2c_host_tx_rx_idx1 899.840s 5531.069us 3 3 100.00
chip_sw_i2c_host_tx_rx_idx2 876.150s 5213.314us 3 3 100.00
chip_sw_i2c_device_tx_rx 3 3 100.00
chip_sw_i2c_device_tx_rx 597.520s 3946.141us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation 6 6 100.00
chip_sw_keymgr_dpe_key_derivation 2963.800s 11301.388us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 3126.670s 11545.422us 3 3 100.00
chip_sw_keymgr_dpe_sideload_kmac 3 3 100.00
chip_sw_keymgr_dpe_sideload_kmac 3343.290s 11921.772us 3 3 100.00
chip_sw_keymgr_dpe_sideload_aes 3 3 100.00
chip_sw_keymgr_dpe_sideload_aes 2550.850s 9732.125us 3 3 100.00
chip_sw_keymgr_dpe_sideload_otbn 0 3 0.00
chip_sw_keymgr_dpe_sideload_otbn 3600.232s 0.000us 0 3 0.00
chip_sw_kmac_enc 9 9 100.00
chip_sw_kmac_mode_cshake 419.720s 3174.242us 3 3 100.00
chip_sw_kmac_mode_kmac 360.900s 2534.192us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 426.280s 3059.281us 3 3 100.00
chip_sw_kmac_app_keymgr_dpe 3 3 100.00
chip_sw_keymgr_dpe_key_derivation 2963.800s 11301.388us 3 3 100.00
chip_sw_kmac_app_lc 15 15 100.00
chip_sw_lc_ctrl_transition 3345.590s 29795.154us 15 15 100.00
chip_sw_kmac_app_rom 3 3 100.00
chip_sw_kmac_app_rom 880.000s 8099.613us 3 3 100.00
chip_sw_kmac_entropy 3 3 100.00
chip_sw_kmac_entropy 2845.160s 9762.232us 3 3 100.00
chip_sw_kmac_idle 3 3 100.00
chip_sw_kmac_idle 414.090s 3358.460us 3 3 100.00
chip_sw_lc_ctrl_alert_handler_escalation 3 3 100.00
chip_sw_alert_handler_escalation 736.980s 4781.074us 3 3 100.00
chip_sw_lc_ctrl_jtag_access 15 15 100.00
chip_tap_straps_dev 1506.240s 11389.209us 5 5 100.00
chip_tap_straps_rma 1082.900s 8526.942us 5 5 100.00
chip_tap_straps_prod 2055.980s 18362.369us 5 5 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 3 3 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 334.860s 3012.970us 3 3 100.00
chip_sw_lc_ctrl_init 15 15 100.00
chip_sw_lc_ctrl_transition 3345.590s 29795.154us 15 15 100.00
chip_sw_lc_ctrl_transitions 15 15 100.00
chip_sw_lc_ctrl_transition 3345.590s 29795.154us 15 15 100.00
chip_sw_lc_ctrl_kmac_req 15 15 100.00
chip_sw_lc_ctrl_transition 3345.590s 29795.154us 15 15 100.00
chip_sw_lc_ctrl_key_div 3 3 100.00
chip_sw_keymgr_dpe_key_derivation_prod 3055.480s 11300.574us 3 3 100.00
chip_sw_lc_ctrl_broadcast 72 81 88.89
chip_sw_rram_rma_unlocked 817.860s 10010.240us 0 3 0.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 499.720s 3221.029us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_dev 1063.860s 6472.684us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_prod 1231.490s 6339.758us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_rma 1289.160s 6732.567us 0 3 0.00
chip_sw_lc_ctrl_transition 3345.590s 29795.154us 15 15 100.00
chip_sw_rram_ctrl_lc_rw_en 820.690s 5340.232us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation 2963.800s 11301.388us 3 3 100.00
chip_sw_rom_ctrl_integrity_check 1772.210s 23169.240us 3 3 100.00
chip_sw_sram_ctrl_execution_main 1257.780s 8033.047us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 2776.760s 23809.062us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 845.660s 4098.872us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 763.110s 4286.842us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 821.590s 4568.252us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 815.020s 5271.877us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 802.350s 3735.779us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 753.110s 4651.759us 3 3 100.00
chip_tap_straps_dev 1506.240s 11389.209us 5 5 100.00
chip_tap_straps_rma 1082.900s 8526.942us 5 5 100.00
chip_tap_straps_prod 2055.980s 18362.369us 5 5 100.00
chip_rv_dm_lc_disabled 224.160s 4164.653us 0 3 0.00
chip_lc_scrap 4 6 66.67
chip_sw_lc_ctrl_rma_to_scrap 741.240s 5377.075us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 555.150s 6769.955us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 729.440s 8275.320us 0 1 0.00
chip_sw_lc_ctrl_rand_to_scrap 982.210s 10919.279us 2 3 66.67
chip_lc_test_locked 0 6 0.00
chip_sw_lc_walkthrough_testunlocks 3600.193s 0.000us 0 3 0.00
chip_rv_dm_lc_disabled 224.160s 4164.653us 0 3 0.00
chip_sw_lc_walkthrough 3 15 20.00
chip_sw_lc_walkthrough_dev 2299.890s 17005.066us 0 3 0.00
chip_sw_lc_walkthrough_prod 2552.130s 21359.254us 0 3 0.00
chip_sw_lc_walkthrough_prodend 2625.420s 19815.030us 3 3 100.00
chip_sw_lc_walkthrough_rma 1581.150s 12461.577us 0 3 0.00
chip_sw_lc_walkthrough_testunlocks 3600.193s 0.000us 0 3 0.00
chip_sw_lc_ctrl_volatile_raw_unlock 9 9 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 431.370s 6411.454us 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 421.110s 5915.251us 3 3 100.00
rom_volatile_raw_unlock 504.780s 5532.595us 3 3 100.00
chip_sw_otbn_op 6 6 100.00
chip_sw_otbn_ecdsa_op_irq 5974.940s 17255.447us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 6057.610s 18989.478us 3 3 100.00
chip_sw_otbn_rnd_entropy 3 3 100.00
chip_sw_otbn_randomness 1248.800s 5707.156us 3 3 100.00
chip_sw_otbn_urnd_entropy 3 3 100.00
chip_sw_otbn_randomness 1248.800s 5707.156us 3 3 100.00
chip_sw_otbn_idle 3 3 100.00
chip_sw_otbn_randomness 1248.800s 5707.156us 3 3 100.00
chip_sw_otbn_mem_scramble 3 3 100.00
chip_sw_otbn_mem_scramble 637.860s 3342.970us 3 3 100.00
chip_otp_ctrl_init 15 15 100.00
chip_sw_lc_ctrl_transition 3345.590s 29795.154us 15 15 100.00
chip_sw_otp_ctrl_keys 9 12 75.00
chip_sw_otbn_mem_scramble 637.860s 3342.970us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation 2963.800s 11301.388us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access 764.060s 5230.965us 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 3600.200s 0.000us 0 3 0.00
chip_sw_otp_ctrl_entropy 9 12 75.00
chip_sw_otbn_mem_scramble 637.860s 3342.970us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation 2963.800s 11301.388us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access 764.060s 5230.965us 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 3600.200s 0.000us 0 3 0.00
chip_sw_otp_ctrl_program 15 15 100.00
chip_sw_lc_ctrl_transition 3345.590s 29795.154us 15 15 100.00
chip_sw_otp_ctrl_program_error 3 3 100.00
chip_sw_lc_ctrl_program_error 865.730s 5629.607us 3 3 100.00
chip_sw_otp_ctrl_hw_cfg0 3 3 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 334.860s 3012.970us 3 3 100.00
chip_sw_otp_ctrl_lc_signals 24 27 88.89
chip_sw_otp_ctrl_lc_signals_test_unlocked0 499.720s 3221.029us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_dev 1063.860s 6472.684us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_prod 1231.490s 6339.758us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_rma 1289.160s 6732.567us 0 3 0.00
chip_sw_lc_ctrl_transition 3345.590s 29795.154us 15 15 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1423.310s 7266.398us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 3 3 100.00
chip_sw_pwrmgr_full_aon_reset 665.120s 6695.789us 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 0 3 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 323.920s 2439.795us 0 3 0.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 0 3 0.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 342.850s 2959.482us 0 3 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 3 3 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 709.960s 7168.372us 3 3 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 0 3 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 675.260s 5206.532us 0 3 0.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1958.250s 24115.203us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 6 6 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1923.050s 15457.337us 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 1030.570s 7741.934us 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 0 3 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 404.120s 3608.220us 0 3 0.00
chip_sw_pwrmgr_wdog_reset 3 3 100.00
chip_sw_pwrmgr_wdog_reset 755.340s 4540.334us 3 3 100.00
chip_sw_pwrmgr_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_full_aon_reset 665.120s 6695.789us 3 3 100.00
chip_sw_pwrmgr_main_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_main_power_glitch_reset 608.450s 4321.531us 3 3 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 3 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 891.080s 9596.431us 0 3 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 665.840s 6013.881us 3 3 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 3 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 376.830s 3378.572us 0 3 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 3 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 781.800s 7139.883us 0 3 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 6 6 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 1171.190s 6592.966us 3 3 100.00
chip_sw_pwrmgr_all_reset_reqs 1656.860s 10426.674us 3 3 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 3 3 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 3303.840s 24987.586us 3 3 100.00
chip_sw_pwrmgr_sleep_disabled 3 3 100.00
chip_sw_pwrmgr_sleep_disabled 337.780s 2973.283us 3 3 100.00
chip_sw_pwrmgr_escalation_reset 89 100 89.00
chip_sw_all_escalation_resets 945.540s 5848.553us 89 100 89.00
chip_sw_rom_access 3 3 100.00
chip_sw_rom_ctrl_integrity_check 1772.210s 23169.240us 3 3 100.00
chip_sw_rom_ctrl_integrity_check 3 3 100.00
chip_sw_rom_ctrl_integrity_check 1772.210s 23169.240us 3 3 100.00
chip_sw_rstmgr_non_sys_reset_info 9 12 75.00
chip_sw_pwrmgr_all_reset_reqs 1656.860s 10426.674us 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 781.800s 7139.883us 0 3 0.00
chip_sw_pwrmgr_wdog_reset 755.340s 4540.334us 3 3 100.00
chip_sw_pwrmgr_smoketest 683.760s 6368.597us 3 3 100.00
chip_sw_rstmgr_sys_reset_info 3 3 100.00
chip_rv_dm_ndm_reset_req 756.480s 5327.482us 3 3 100.00
chip_sw_rstmgr_cpu_info 3 3 100.00
chip_sw_rstmgr_cpu_info 893.840s 5488.697us 3 3 100.00
chip_sw_rstmgr_sw_req_reset 3 3 100.00
chip_sw_rstmgr_sw_req 605.250s 3441.717us 3 3 100.00
chip_sw_rstmgr_alert_info 3 3 100.00
chip_sw_rstmgr_alert_info 1926.210s 12093.606us 3 3 100.00
chip_sw_rstmgr_sw_rst 3 3 100.00
chip_sw_rstmgr_sw_rst 341.730s 2709.193us 3 3 100.00
chip_sw_rstmgr_escalation_reset 89 100 89.00
chip_sw_all_escalation_resets 945.540s 5848.553us 89 100 89.00
chip_sw_rstmgr_alert_handler_reset_enables 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 2013.950s 8153.050us 3 3 100.00
chip_sw_nmi_irq 3 3 100.00
chip_sw_rv_core_ibex_nmi_irq 959.360s 4350.380us 3 3 100.00
chip_sw_rv_core_ibex_rnd 3 3 100.00
chip_sw_rv_core_ibex_rnd 1037.770s 4921.055us 3 3 100.00
chip_sw_rv_core_ibex_address_translation 3 3 100.00
chip_sw_rv_core_ibex_address_translation 387.770s 2636.827us 3 3 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 0 3 0.00
chip_sw_rv_core_ibex_icache_invalidate 3600.200s 0.000us 0 3 0.00
chip_sw_rv_core_ibex_fault_dump 3 3 100.00
chip_sw_rstmgr_cpu_info 893.840s 5488.697us 3 3 100.00
chip_sw_rv_core_ibex_double_fault 3 3 100.00
chip_sw_rstmgr_cpu_info 893.840s 5488.697us 3 3 100.00
chip_sw_rv_core_ibex_mcounteren_writable 3 3 100.00
chip_sw_rv_core_ibex_mcounteren_writable 363.650s 2737.078us 3 3 100.00
chip_jtag_csr_rw 1 3 33.33
chip_jtag_csr_rw 1807.390s 14307.113us 1 3 33.33
chip_jtag_mem_access 3 3 100.00
chip_jtag_mem_access 2664.810s 19500.176us 3 3 100.00
chip_rv_dm_ndm_reset_req 3 3 100.00
chip_rv_dm_ndm_reset_req 756.480s 5327.482us 3 3 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 3 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 476.310s 3315.923us 0 3 0.00
chip_rv_dm_access_after_wakeup 0 3 0.00
chip_sw_rv_dm_access_after_wakeup 327.650s 2861.147us 0 3 0.00
chip_sw_rv_dm_jtag_tap_sel 5 5 100.00
chip_tap_straps_rma 1082.900s 8526.942us 5 5 100.00
chip_rv_dm_lc_disabled 0 3 0.00
chip_rv_dm_lc_disabled 224.160s 4164.653us 0 3 0.00
chip_sw_plic_all_irqs 9 9 100.00
chip_plic_all_irqs_0 948.040s 5228.670us 3 3 100.00
chip_plic_all_irqs_10 610.430s 4118.808us 3 3 100.00
chip_plic_all_irqs_20 627.580s 4071.337us 3 3 100.00
chip_sw_plic_sw_irq 3 3 100.00
chip_sw_plic_sw_irq 400.110s 3413.541us 3 3 100.00
chip_sw_timer 3 3 100.00
chip_sw_rv_timer_irq 446.280s 3398.476us 3 3 100.00
chip_sw_spi_device_flash_mode 3 3 100.00
rom_e2e_smoke 5319.610s 14991.660us 3 3 100.00
chip_sw_spi_device_pass_through 3 3 100.00
chip_sw_spi_device_pass_through 810.750s 6349.882us 3 3 100.00
chip_sw_spi_device_pass_through_collision 0 3 0.00
chip_sw_spi_device_pass_through_collision 405.230s 3037.657us 0 3 0.00
chip_sw_spi_device_tpm 3 3 100.00
chip_sw_spi_device_tpm 489.540s 2895.276us 3 3 100.00
chip_sw_spi_host_tx_rx 3 3 100.00
chip_sw_spi_host_tx_rx 465.070s 2886.351us 3 3 100.00
chip_sw_sram_scrambled_access 6 6 100.00
chip_sw_sram_ctrl_scrambled_access 764.060s 5230.965us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 667.570s 4003.597us 3 3 100.00
chip_sw_sleep_sram_ret_contents 0 6 0.00
chip_sw_sleep_sram_ret_contents_no_scramble 391.360s 2672.105us 0 3 0.00
chip_sw_sleep_sram_ret_contents_scramble 399.490s 2864.139us 0 3 0.00
chip_sw_sram_execution 3 3 100.00
chip_sw_sram_ctrl_execution_main 1257.780s 8033.047us 3 3 100.00
chip_sw_sram_lc_escalation 95 106 89.62
chip_sw_all_escalation_resets 945.540s 5848.553us 89 100 89.00
chip_sw_data_integrity_escalation 946.050s 5277.057us 6 6 100.00
chip_sw_sysrst_ctrl_reset 6 6 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 1171.190s 6592.966us 3 3 100.00
chip_sw_sysrst_ctrl_reset 2274.430s 22387.211us 3 3 100.00
chip_sw_sysrst_ctrl_inputs 3 3 100.00
chip_sw_sysrst_ctrl_inputs 377.050s 2748.352us 3 3 100.00
chip_sw_sysrst_ctrl_outputs 3 3 100.00
chip_sw_sysrst_ctrl_outputs 531.180s 3464.848us 3 3 100.00
chip_sw_sysrst_ctrl_in_irq 3 3 100.00
chip_sw_sysrst_ctrl_in_irq 746.790s 4298.388us 3 3 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 3 3 100.00
chip_sw_sysrst_ctrl_reset 2274.430s 22387.211us 3 3 100.00
chip_sw_sysrst_ctrl_sleep_reset 3 3 100.00
chip_sw_sysrst_ctrl_reset 2274.430s 22387.211us 3 3 100.00
chip_sw_sysrst_ctrl_ec_rst_l 3 3 100.00
chip_sw_sysrst_ctrl_ec_rst_l 4329.570s 20463.537us 3 3 100.00
chip_sw_sysrst_ctrl_flash_wp_l 3 3 100.00
chip_sw_sysrst_ctrl_ec_rst_l 4329.570s 20463.537us 3 3 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 3 6 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 627.040s 5331.418us 3 3 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.200s 0.000us 0 3 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 215.460s 2399.000us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 277.960s 2189.341us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 528.250s 3207.866us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 691.220s 3870.578us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1895.000s 7621.023us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 10301.610s 31749.819us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 3458.790s 12590.064us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 386.660s 3254.790us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 3 3 100.00
chip_sw_aes_masking_off 436.610s 2684.181us 3 3 100.00
chip_sw_rv_core_ibex_lockstep_glitch 3 3 100.00
chip_sw_rv_core_ibex_lockstep_glitch 369.730s 2823.007us 3 3 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 0 1 0.00
chip_sw_coremark 18000.188s 0.000us 0 1 0.00
chip_sw_power_max_load 3 3 100.00
chip_sw_power_virus 2090.210s 6699.772us 3 3 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 159.220s 2072.481us 0 1 0.00
rom_e2e_jtag_debug_dev 124.930s 2202.909us 0 1 0.00
rom_e2e_jtag_debug_rma 110.560s 1696.533us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 138.220s 1858.810us 0 1 0.00
rom_e2e_jtag_inject_dev 166.310s 2264.827us 0 1 0.00
rom_e2e_jtag_inject_rma 158.770s 2621.341us 0 1 0.00
rom_e2e_self_hash 0 3 0.00
rom_e2e_self_hash 49.955s 0.000us 0 3 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 3 0.00
chip_sw_clkmgr_jitter_frequency 564.550s 3729.951us 0 3 0.00
chip_sw_edn_boot_mode 3 3 100.00
chip_sw_edn_boot_mode 622.360s 2899.511us 3 3 100.00
chip_sw_edn_auto_mode 3 3 100.00
chip_sw_edn_auto_mode 1927.000s 6286.482us 3 3 100.00
chip_sw_edn_sw_mode 3 3 100.00
chip_sw_edn_sw_mode 2283.040s 8735.432us 3 3 100.00
chip_sw_edn_kat 3 3 100.00
chip_sw_edn_kat 472.190s 2343.573us 3 3 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 382.470s 2787.225us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 3 3 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 624.880s 5493.374us 3 3 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 3 3 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 636.180s 4700.128us 3 3 100.00
chip_sw_all_resets 3 3 100.00
chip_sw_pwrmgr_all_reset_reqs 1656.860s 10426.674us 3 3 100.00
chip_sw_rom_ctrl_digests 3 3 100.00
chip_sw_kmac_app_rom 880.000s 8099.613us 3 3 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 159.220s 2072.481us 0 1 0.00
rom_e2e_jtag_debug_dev 124.930s 2202.909us 0 1 0.00
rom_e2e_jtag_debug_rma 110.560s 1696.533us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 2 3 66.67
chip_sw_rv_dm_access_after_escalation_reset 751.460s 5524.769us 2 3 66.67
chip_sw_plic_alerts 89 100 89.00
chip_sw_all_escalation_resets 945.540s 5848.553us 89 100 89.00
tick_configuration 0 3 0.00
chip_sw_rv_timer_systick_test 7200.213s 0.000us 0 3 0.00
counter_wrap 0 3 0.00
chip_sw_rv_timer_systick_test 7200.213s 0.000us 0 3 0.00
chip_sw_spi_device_output_when_disabled_or_sleeping 0 3 0.00
chip_sw_spi_device_pinmux_sleep_retention 383.910s 2891.651us 0 3 0.00
chip_sw_uart_watermarks 5 5 100.00
chip_sw_uart_tx_rx 797.130s 4615.560us 5 5 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 5665.570s 18253.206us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 3 22 13.64
chip_sw_rstmgr_rst_cnsty_escalation 78.180s 10.360us 0 3 0.00
chip_sw_otp_ctrl_rot_auth_config 128.980s 1838.647us 0 1 0.00
chip_sw_otp_ctrl_descrambling 428.130s 3341.029us 3 3 100.00
chip_sw_pwrmgr_lowpower_cancel 334.890s 3220.829us 0 3 0.00
chip_sw_pwrmgr_sleep_wake_5_bug 16.612s 0.000us 0 3 0.00
ate_bootstrap_flash_erase 1253.090s 10010.220us 0 3 0.00
ate_bootstrap_one_frame 10800.215s 0.000us 0 3 0.00
ate_bootstrap_disjoint 10800.190s 0.000us 0 3 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 90 test runs
chip_sw_alert_handler_lpg_sleep_mode_alerts 84295578437276288234858553977075040604259462597852671212106394828760454544586 373
UVM_INFO @ 2553.699025 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 30891779320679450334204171879729001039740601658206784083314317406784119053728 378
UVM_INFO @ 2547.531247 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 2539429307170447639270545554056049373339618708940631989313920569451549916403 373
UVM_INFO @ 3094.207250 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 102104393806248665137805808291504941500515956354168072792998449774516329560736 373
UVM_INFO @ 2493.610040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 108174248083605770666567854795752112189639546762544506677158283120670497739666 373
UVM_INFO @ 2225.863780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 106950667781900457617062992597579699032861472613195070766683932466644778820103 373
UVM_INFO @ 2438.932971 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 23283731448571228159381747410670698515687978448058917147575278524496073055391 373
UVM_INFO @ 2363.078190 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 24306329996532681481399747526586859335220939633929075654011428338243800715787 373
UVM_INFO @ 2417.945692 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 81485594528582967464191617851169452518771038038512081073729869086159413470971 373
UVM_INFO @ 3112.193519 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 30357215254903058318595574038692551401094035182134687316964528471297639429455 373
UVM_INFO @ 2742.566482 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 102922024966954173839706408381885693819898300022866509469074516907365293696603 373
UVM_INFO @ 3038.385340 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 100667501240359830708668786889471481793323776622955806308219050022867846833765 373
UVM_INFO @ 2196.271880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 56168006380551403104634377795808733240903635280407227398111796613376099903906 373
UVM_INFO @ 2460.505077 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 96992706698395065655385604657693697166103639335819551631580817799601481635464 373
UVM_INFO @ 2600.396780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 46570492770943321303299677962045090324274078598201115614641687724549683577375 373
UVM_INFO @ 2367.103120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 50320220891477281845403796764732459279607079262243953082790878234108744120338 373
UVM_INFO @ 2983.566096 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 60526355911155939420357633330060787637477529825748512280777633253593846652924 373
UVM_INFO @ 2932.693902 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 1132500119113396416196926728125746807586438291390592898027263141223757636643 373
UVM_INFO @ 2558.622840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 109678864756688676946597472563525106549453012552392660358605133332400273513678 373
UVM_INFO @ 2836.152820 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 59672349239410250880552409794297847145979721486404907824130962699955485288600 373
UVM_INFO @ 2147.809139 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 97540924636301362959380643887151038125290644572792198268645513221958814921127 373
UVM_INFO @ 3032.628100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 90836774566568873768903709731152858394645173985256655058407665948675931183653 373
UVM_INFO @ 2868.491700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 70918636619649439377780800928023713595703326871055054454742218223652300122825 373
UVM_INFO @ 2884.217168 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 91455738225818558859198323827166670543808824844955666575507494526366067942506 373
UVM_INFO @ 2388.313331 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 94414147925153674831939940674128409082717093888738587213670041571650886510361 373
UVM_INFO @ 2666.672462 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 96803626678531935783556088479963706808047236206372844310366897992951287004994 373
UVM_INFO @ 2907.849000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 11958487817841671014408136889807777783053539786841145678957738746922196843016 373
UVM_INFO @ 2878.051854 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 57172178348821940439064975966175693090430213178665235926289238010174023804520 373
UVM_INFO @ 2637.530575 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 38020633198975302090274320901492553236355838703805476417507651519874731368684 373
UVM_INFO @ 3036.728958 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 27412985559988856536423858475545019415590652656649862846077794619949434462472 373
UVM_INFO @ 2779.808102 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 56475142937641645502010567255338837910570045390348107955295396770281560366141 373
UVM_INFO @ 2269.012440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 100275242963054085155617240784842843943172076164200965885558417466912067725230 373
UVM_INFO @ 2945.191537 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 8820754147373558134753450331481801487678930752671781891636159420251764452042 373
UVM_INFO @ 2555.106568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 98659587942276483517587741949096393611042632841007440837375578193292344271711 373
UVM_INFO @ 2310.767917 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 68906588857013059586661420392643528719709493325103852027644966326435075522631 373
UVM_INFO @ 2664.971364 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 57996131131555206576171606334408240826271772478938091662104871622969144549035 373
UVM_INFO @ 3020.759153 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 85775500077397588359024459943509713870125194844496820904902748002425436775142 373
UVM_INFO @ 2574.181730 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 40471019186241765990911406683225406287107575972427661913631246576024880464805 373
UVM_INFO @ 2840.832981 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 86396169995210336304467545485754242227415432167627884590319079930961897554608 373
UVM_INFO @ 2350.040800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 48142573495714529769040049928885550739425401399432149905533920720135797386418 373
UVM_INFO @ 2566.118936 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 39933266105023262521820936278107407241520704236134734279642702634065288416128 373
UVM_INFO @ 2946.013514 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 2420453093657752063374894825883219737904406039913171286387405781958827813741 373
UVM_INFO @ 2941.394578 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 52422206040239092603394860669861698474468427034877138755082608224325067854576 373
UVM_INFO @ 2457.184912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 101821267196716020762445849539759046832288604764859207169775978859655045901964 373
UVM_INFO @ 2686.644860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 32679573957740362487136586185290692883458082103179721403492737299895022655019 373
UVM_INFO @ 2750.158500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 59214407907933400427042796998958657568812773422021909638154610835069234007189 373
UVM_INFO @ 2141.283194 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 65687548358281395024274279658371118533415013763823076847490952622882928489415 373
UVM_INFO @ 2790.257378 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 92577628816580362127599266513356946708662634947724413541628456486982680203724 373
UVM_INFO @ 2733.465900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 108916201325484869621512188076215163312946241918451645091528618733827669812576 373
UVM_INFO @ 2265.189888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 74595750727926574666836898669646394198742368779301274629576012200156848154595 373
UVM_INFO @ 2594.300895 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 38103871153665266052892119408076657277622424517503244230421656892885753166523 373
UVM_INFO @ 2438.680964 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 110208215624388488332201690377434323081420403219898125136538809200871330491881 373
UVM_INFO @ 2984.168408 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 53328910237194419193021631856682056225734504313723821284919732486954799527779 373
UVM_INFO @ 2489.365504 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 30018651080510648563980613791713324291062980539637049201406140822353125344645 373
UVM_INFO @ 3086.512286 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 49149639887196239728668739341381907993555215764073583025595631217961375139773 373
UVM_INFO @ 2678.469343 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 70914415761357658569054819388623841775026192758622204150441753604401457313938 373
UVM_INFO @ 2896.595737 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 19849887090232785452337546099264907201925753628169969422200488817335852802083 373
UVM_INFO @ 2705.889765 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 42702478756567201667060921778010590083391941861066950836763206789809566015261 373
UVM_INFO @ 2311.267248 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 22061690152869197554491801814312098159405757688594103566318907425273836299765 373
UVM_INFO @ 2400.128968 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 93519788208734333916982456600032987652826633698214245616325528561823337382450 373
UVM_INFO @ 2520.835852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 79805663844469098885186231099017384567594672633261241432998831320424811459012 373
UVM_INFO @ 2828.998286 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 33305969147740697359242770050550146462949330471292748106025090816464438154176 373
UVM_INFO @ 2372.457221 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 67268135830766859075415090227819433288970062550429390209763541305356527436881 373
UVM_INFO @ 2543.126838 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 23561946173602619193527854758415058154449034205198030679365835326437878064517 373
UVM_INFO @ 2638.766220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 6584026107685491706118716166317734928535773404756591053933260048623526044016 373
UVM_INFO @ 2709.248688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 96581819107861044511200094178211670274321664694115778361918517129400765812285 373
UVM_INFO @ 2551.042704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 113577115173944445678920512103951382721550256511514706758270640281876668931200 373
UVM_INFO @ 2757.351750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 32111519109655294715365597324586548480456846912423151827983942880870436117887 373
UVM_INFO @ 2751.110956 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 76099317022342792598305148167808466779276459289008375640838368772026831347498 373
UVM_INFO @ 2589.997362 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 103365286261724456737855166537784023342299362187590938783244037682260782878018 373
UVM_INFO @ 2999.572784 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 65626816653275525735032555644304049864846148507210534249530303988032563040694 373
UVM_INFO @ 2729.767628 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 19519534048120080578834601902647313495547822007612881448821403920501494674484 373
UVM_INFO @ 2933.577718 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 37927448115378726732817357254655261531888552663668504506970293755706463812566 373
UVM_INFO @ 2565.065120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 107979332081777914733725317510435858559909827007630128985800255520012344434820 373
UVM_INFO @ 2279.831138 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 53472447074038994184945664781478291660533081669557715989229057843161149126930 373
UVM_INFO @ 2359.805970 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 76148861388092365559007257653234768841247544934546325680065101480734410203469 373
UVM_INFO @ 2697.226184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 69417540400148028236494088413343302928631148071916815378041595221438781639564 373
UVM_INFO @ 2268.896560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 11598635810829411571300231012226853696165503039055393607007671997719448087711 373
UVM_INFO @ 2847.030165 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 72783207187846719920199355212570933230835237556390880588779504213907956369633 373
UVM_INFO @ 2860.720477 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 28879231169890076707266941710053194746063436019364400225307191073137922902689 373
UVM_INFO @ 2954.890477 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 72974980415209024785712209541530499957037873175289871036403433040011533752260 373
UVM_INFO @ 2746.180965 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 96106491369783119897814353678922808326023731695934550856663867654985092187666 373
UVM_INFO @ 2726.762920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 84116083933167247559681854605584819494155546525385866260742743791530786869349 373
UVM_INFO @ 2671.925330 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 40147133863141249623360544837572535877959880241398762688082194036190699190519 373
UVM_INFO @ 2273.995200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 114443002545544741678622691003885993523417563738773826773626693093873616110681 373
UVM_INFO @ 2381.101160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 74740230332331815607058074778763749980459662542349574415730158541884566106878 373
UVM_INFO @ 2584.154885 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 96454292000557714357647856521792975104479698645006477865236817105194244822220 373
UVM_INFO @ 2645.906401 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 70233969989581949609921155590550459662617724484430066422197376314614206645900 373
UVM_INFO @ 3059.893810 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 85791624993186489337429272380743193854965999590042745611888905898230310431775 373
UVM_INFO @ 2826.946668 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 23182017693158737841335239881069066995324364394167262103566916785374949659446 373
UVM_INFO @ 2284.647962 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:254) scoreboard [scoreboard] alert fatal has unexpected signal int error 47 test runs
chip_sw_sleep_pin_retention 103369345508047483039904016063776713836296979434896009991081487600394922150741 379
UVM_INFO @ 2534.867112 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pinmux_sleep_retention 60559383174643720206558404683587983768097582266980644917332400572613027503906 374
UVM_INFO @ 2952.111952 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_reset_reqs 88720664925551756463229302360676657392925058087474346437376592992937018433018 392
UVM_INFO @ 7596.239388 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 31797607669272311721879306393598060382162322952004526161799336428559133189357 377
UVM_INFO @ 3608.219688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_por_reset 43057536461901900320503017198031156361419701062533585999182642041267316982422 388
UVM_INFO @ 5206.532364 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 92330832115706569228042957018592520835089209418988036788523510172621933740531 379
UVM_INFO @ 3049.447932 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_no_scramble 98521233360268889665062829312635564516370332263169366581035878547438573719179 377
UVM_INFO @ 2672.104588 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_scramble 54398946065432314320068870051428821504799785709098733286217249305089131617934 381
UVM_INFO @ 2985.983104 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 35419911622257773298925900629193523064205752043362447020986410447366312583131 372
UVM_INFO @ 2137.378616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_sleep_frequency 26222839689909308251593664584216509693566782898465999066102528325659650024219 407
UVM_INFO @ 4103.415856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_wake_ups 46378593550938493454244903875980426485520958803486894686590838795110786434425 374
UVM_INFO @ 2737.000644 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_lowpower_cancel 102502918372103772172952957246592142756151537427557961753214276594118179362577 372
UVM_INFO @ 3220.828680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_wake_ups 98842895864555287162021928619235541284633019625535874432522755037403434406671 373
UVM_INFO @ 2974.187080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rv_dm_access_after_wakeup 6420790560338049292241505667486082574715753163395854280888147528847891644335 390
UVM_INFO @ 2378.991184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_sleep_load 6951314585919056385038722071290678431762899555903520227176477720416914088895 387
UVM_INFO @ 4041.732684 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_pin_wake 54832611349767483354928678852216070569629818340921333682676933383169324709261 382
UVM_INFO @ 2705.709392 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_pin_retention 97075498774032672183237014997466135345457304674925447266850196888143238824478 379
UVM_INFO @ 3163.562766 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pinmux_sleep_retention 13440774591118336459367068506809569919289914097254446960745013993241687972282 374
UVM_INFO @ 2802.886632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_reset_reqs 22175907826992160843249985660405789144451663749890740621463119357020418351119 392
UVM_INFO @ 7001.690478 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 101894816592580623195133349142482927235399999195449851075195070740754643471361 377
UVM_INFO @ 3216.645696 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_por_reset 29040070691958303579074882606866144812138536933934524115559050871608090132689 388
UVM_INFO @ 5103.499448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 93484772907573933403604267836120884131983283159187841422879144244872994799269 379
UVM_INFO @ 3897.852496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_pings 72322119230582962313265447924785961931046530298606634849220007322143719063837 374
UVM_INFO @ 2993.263336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_no_scramble 16544331895456870888451771238714934133502347706053562954056272264880676809548 377
UVM_INFO @ 3409.384972 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_scramble 31970840545899203724959648611890016432032191931940523451220107640381359738096 381
UVM_INFO @ 2864.139114 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 55594651187896361983354592827672727094917092939959847025556138842868599403726 372
UVM_INFO @ 2685.272840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_sleep_frequency 105708457536462583786713891731302889805054907537848384661639407678222629870273 407
UVM_INFO @ 4083.255944 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_wake_ups 81574761498982992634033006142336509546815616523003216246022567437340065175978 374
UVM_INFO @ 2753.244010 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_lowpower_cancel 56533122368163405849631688200763090028498536327567204862717586736834603326160 372
UVM_INFO @ 2662.747626 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_wake_ups 45552773859167073794255802920820446760328260079730584476801875821304987708827 373
UVM_INFO @ 2439.794972 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rv_dm_access_after_wakeup 86993171589905504009633871262473884738783868424547998263703928938991775672355 390
UVM_INFO @ 2180.658528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_pin_wake 103727039290473523871204170877465888676670076675937644102266440268999343152620 382
UVM_INFO @ 2773.767192 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_pin_retention 30307960775832409306698271576226743443329977245417009850271689706891009492840 379
UVM_INFO @ 3340.093974 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pinmux_sleep_retention 107102461890495700857881171380643747675585108839668690085329002619224266398037 374
UVM_INFO @ 2891.651056 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_reset_reqs 42687813882861618586895418504575543186570759703707227183252615368040280224163 392
UVM_INFO @ 7139.882682 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 34684361286165844753116945465893786947744689036637608878512972097258141550345 377
UVM_INFO @ 4200.914184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_por_reset 39462187780568950300631478028972015148195552573444837113425700684529056013646 388
UVM_INFO @ 4836.259080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 48389748844869700635035385671343756394427521638679776286135639855989461098760 418
UVM_INFO @ 9596.430986 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_no_scramble 11274159757763741047365854245385958582176906537852319842399333734460430734972 377
UVM_INFO @ 3398.253516 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_scramble 87840933567304560152546353529262645095324036529102034665096008479691837302951 381
UVM_INFO @ 2887.944536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 94526656414887530515491247685990808736730332441395758413379850807136942631442 372
UVM_INFO @ 2630.977522 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_sleep_frequency 12120465704283357138884158470093581247719045300941518468740537646680527396637 407
UVM_INFO @ 4760.357724 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_wake_ups 24066189028863610808965302515138499051343005267269556329148810060011514268124 374
UVM_INFO @ 2959.482288 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_lowpower_cancel 28260358495238517494569240262964812896819071626710707937567892584496422809157 372
UVM_INFO @ 3104.490704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_wake_ups 51973989337672156847811180476954436179412860456765463969928584373757059479344 373
UVM_INFO @ 2509.038264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rv_dm_access_after_wakeup 5127971529590386067408495463793419531547635125283394150531090761367752266306 390
UVM_INFO @ 2861.146584 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_sleep_load 10930080614342755869531497309092683581852871227737062955492266715538823848123 387
UVM_INFO @ 3699.519992 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 40 test runs
chip_csr_aliasing 88472157037857489939397678793539917246240634047047979257556892716353890063734 None
chip_sw_uart_tx_rx_bootstrap 96355530126362206982824298022324127021386373783338204064190298368139540315852 None
chip_sw_exit_test_unlocked_bootstrap 52371100642813522844447208924701047076274801957765705747638993841786989405087 None
chip_sw_lc_walkthrough_testunlocks 75991722762361704273396072195164531157568097150662944180846355669428742036110 None
chip_sw_rv_timer_systick_test 22642195981023509993891839931530512509006942993723888268747968635019251187604 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 105564459354926837271790965421009132193226014709166373052554312517023534461497 None
chip_sw_alert_handler_reverse_ping_in_deep_sleep 28280262306902082311921499806714043504782640295656872467894194467737788987295 None
chip_sw_keymgr_dpe_sideload_otbn 83412354621857966988478607916969798403188279311492604438643564523491099887524 None
chip_sw_coremark 64301189734487216383470536471941380191414874885396383402314283306000107201835 None
chip_tl_errors 39742176106608119864562899337724955910765174638064437311631093842464188987915 None
chip_sw_rv_core_ibex_icache_invalidate 78268073252064054323412634652148128383338981328606126502672511666836196798443 None
ate_bootstrap_one_frame 85042753030294437209340187334451803694533540060295620671921042028490504755017 None
ate_bootstrap_disjoint 12845174049552982703895523018704113230709055558486577438174224767924662965515 None
chip_sw_uart_tx_rx_bootstrap 61550205819872543524967173044297612514975982266452275680036185657100734207385 None
chip_sw_exit_test_unlocked_bootstrap 111389025517818838156427565317779390023944514650498541489352997923727455788184 None
chip_sw_rv_timer_systick_test 18414113003111839479144808816317679864366769502803436991692005595863978538399 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 12626988798282107130281469993833194436804604302385909479218399844908243068645 None
chip_sw_alert_handler_reverse_ping_in_deep_sleep 62000593901688585939819365086962383286648128122032059978116188008824850849571 None
chip_sw_keymgr_dpe_sideload_otbn 28517576887666253993718645403939257437413398938097361373060334643806396603804 None
chip_tl_errors 10097884253486331115176698392050405996334047421705547315537453626358187800987 None
chip_sw_rv_core_ibex_icache_invalidate 67772315346417653936066968514948465209706865015647354349612745045153609132035 None
ate_bootstrap_one_frame 90107739480133653407938223365939047616222557124406123627949618304072219651962 None
ate_bootstrap_disjoint 109870793670270263300580567560010009463744204051938474953396097440571445152532 None
chip_sw_uart_tx_rx_bootstrap 32001116644496372689970717883956852301970655200923684929109248595645423799791 None
chip_sw_exit_test_unlocked_bootstrap 89497300537629047674557111544366854659204137674331344027500758215180437790359 None
chip_sw_lc_walkthrough_testunlocks 72749706574249600455389579990308492242056778611901453142429519030440291991112 None
chip_sw_rv_timer_systick_test 71608104737273500437693932634612980618349681442331743318706778805463722262356 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 8733283909737161790687470128561713017209834722186623379201285260040390789162 None
chip_sw_alert_handler_reverse_ping_in_deep_sleep 61365964927928233202711606391583525273998275758112004473313601818856150900357 None
chip_sw_hmac_multistream 51578851413638085221324711560292352404103782005863199897034627855882800097790 None
chip_sw_keymgr_dpe_sideload_otbn 6916078753821835204243096211054970806805993324677991580250250737010521395785 None
chip_sw_rv_core_ibex_icache_invalidate 91805485728333831762728447397750505510826583462966150291721922315322683083948 None
ate_bootstrap_one_frame 29329137230161930973970160696641059188363891829620496504984781948066928337516 None
ate_bootstrap_disjoint 80759429289666982167870912539004572247466017824216334046400984016923719352329 None
chip_tl_errors 24648420094200704509489719007280098320368839484391367841841210144190517008765 None
chip_tl_errors 109695612941840383436877815027987471829997940877924495602844105917292648771597 None
chip_tl_errors 28580373661130731994335552078318270591306944213504732849940975155357069664967 None
chip_tl_errors 65452525296000461936292490688371536131703166849863663270796230156731898359768 None
chip_tl_errors 64661142902158175868824798975602655406049138376708364536478087869996067971152 None
chip_tl_errors 115495599750610125901624076326124911251935729207396032921955789724319914065890 None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 9 test runs
chip_sw_lc_walkthrough_dev 38983780446723440008378895039924678732090326921128993799880245514291334859980 433
UVM_INFO @ 16420.516426 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 87454361496454265038014947737152889878684061984304385088611492874327096475421 433
UVM_INFO @ 18714.958076 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 11393654782917525798963635367287591031231749907061483338079358243364089047012 405
UVM_INFO @ 12461.577400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_dev 53855833042062655147832400778468750036332068610989394360392775910463769108693 433
UVM_INFO @ 17905.967996 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 100324615628206238569483796495039987935093570296810154511367308260810800938391 433
UVM_INFO @ 17859.453570 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 100325503858027682328646139823238780479362097020784332120390039806808331246319 405
UVM_INFO @ 13069.596559 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_dev 97658848693658254948719679703541642337402786487833892185740824636463562153682 433
UVM_INFO @ 17005.065700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 106067322371738993215121556723435781575964478299454187663404433245839801322963 433
UVM_INFO @ 21359.253780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 90157219195537465601418862989016960391237103745100186726658766716675215810118 405
UVM_INFO @ 11272.773778 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access 7 test runs
chip_sw_otp_ctrl_rot_auth_config 6207319797513935812076996667714112342361642758816956279859236681259747035652 379
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 2000058772465761951114261252534559278975453153703308036903970055020455105666 403
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 73114431518653855234497699688079377654168882977932074091442648745592770532966 379
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 61821335088894314492170696917139625441189435177872954051625545775560018650907 379
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 46261062240619655044079066174134679928135425625156726360425875472475155673041 381
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 5015445600600733274806943652805464709403776222662767872872466646616297835385 403
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 87271247477450680508603820045720533200531770978330434185562331483742776163440 403
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 6 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 33701644078026486253096539427740497272056354352416842694536933912298650229857 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 1127641348218638005609007368551437785038992584485950201230745703918851913114 None
---- STDERR ----
Another command (pid=194986) is running. Waiting for it to complete on the server (server_pid=194999)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_sleep_wake_5_bug 41112187701573258466259125526348269899355538154851526284500529708828157168905 None
---- STDERR ----
Another command (pid=200451) is running. Waiting for it to complete on the server (server_pid=194999)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 28270094507096393055577479049010177662367947611953844084017935631841760670423 None
Another command (pid=197744) is running. Waiting for it to complete on the server (server_pid=194999)...
Another command (pid=222215) is running. Waiting for it to complete on the server (server_pid=194999)...
Another command (pid=230241) is running. Waiting for it to complete on the server (server_pid=194999)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_sleep_wake_5_bug 71739143655630275092592012077405712163516378177713987165254727670484846678436 None
---- STDERR ----
Another command (pid=1129369) is running. Waiting for it to complete on the server (server_pid=194999)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 28575050401488180074716423012715096190401976471310447700538057203397615490368 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 5 test runs
chip_sw_otp_ctrl_escalation 103039486054982184887829904796203753585676862525204878302808887729922204183331 380
UVM_ERROR @ 2787.225254 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2787.225254 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 85592105003340560831130688943723924389331804180876372981412651400877075671420 383
UVM_ERROR @ 2192.569858 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2192.569858 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 55835850285588271747765022959273574648128608285548266698165659811465834593063 383
UVM_ERROR @ 3002.651648 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3002.651648 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 12897717775312591340499672823247620466265035591905959082130415835303197315274 383
UVM_ERROR @ 3372.058464 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3372.058464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 94499040578567516217714947668621541821154219228577701566388446186050904060780 383
UVM_ERROR @ 2529.823632 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2529.823632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error 5 test runs
chip_sw_alert_handler_lpg_sleep_mode_pings 22707195998524228063768897843605966265290366672294864000379099918044664207153 373
UVM_INFO @ 2857.207118 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_entropy 7729100713093136524387039184287564821131288872678469488866063663373635435279 482
UVM_INFO @ 3177.551130 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_entropy 111321463174015570659973444082490887688266101919732132420402790249874059941111 480
UVM_INFO @ 3036.817488 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_pings 59841556866413263777931825027256776005995445506051381724290530652591770052952 374
UVM_INFO @ 2711.140408 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_entropy 42307067868209607740763837227129724037616857477663831095767364282344193373737 486
UVM_INFO @ 2808.685704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal triggered unexpectedly 4 test runs
chip_same_csr_outstanding 108680183784646657688124887402340013429380152738683955060666917609607371846508 282
UVM_INFO @ 8616.528660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_same_csr_outstanding 21653378363829682222185201879906461264133329813203557453297776205596590233263 282
UVM_INFO @ 5270.252780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 97209608513445295667674403633804144669632541940148769490363735439245123175853 382
UVM_INFO @ 3462.569852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 93127676308760665721757955974823234984948877941068124366348549114444098436276 382
UVM_INFO @ 2862.802464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr.u_d0_spi_host*.leaf_rst_path 3 test runs
chip_sw_rstmgr_rst_cnsty_escalation 35901208964669844586283640554280342759597731150657373021754141028513884690032 365
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_rst_cnsty_escalation 50001915130187398823046310505114679646268943321922702279939908709449795813280 365
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_rst_cnsty_escalation 35945394076218216937893592076715008734171823860164354515886521833713363613827 365
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 3 test runs
chip_sw_spi_device_pass_through_collision 22811602167771388420136277437353553899484212918270235070005105539141294062328 391
UVM_INFO @ 3037.657496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pass_through_collision 20663295967102474824302717562191437513796792161371052889427550551998745792343 391
UVM_INFO @ 3061.472618 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pass_through_collision 6133436670535673244844355499119556323993093817224433255387529803529871461343 391
UVM_INFO @ 3092.087512 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rram_rma_unlocked_vseq.sv:162) [chip_sw_rram_rma_unlocked_vseq] wait timeout occurred! 3 test runs
chip_sw_rram_rma_unlocked 55065578840644606706976725631587807067705564873919267923409562718632518691122 337
UVM_INFO @ 10010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rram_rma_unlocked 104607477243989792506230767877687004893383453257778808544955465952938358236597 337
UVM_INFO @ 10010.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rram_rma_unlocked 72553136572751690934250711440157030612606170165887463874128262104079591017475 337
UVM_INFO @ 10010.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 3 test runs
chip_sw_otp_ctrl_lc_signals_rma 27456890769609242453517221501199134731776135982086397697139903087493660068383 404
UVM_INFO @ 5709.142300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otp_ctrl_lc_signals_rma 63632215004899288680416262768217388195329413761010655658005707882235160639076 404
UVM_INFO @ 6732.567464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otp_ctrl_lc_signals_rma 20543024098799413749911216589832812127382028672928894555771990719399750602147 404
UVM_INFO @ 6643.309516 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 3 test runs
chip_sw_pwrmgr_sleep_power_glitch_reset 70578031173165924867065585182495342784562734181525940642222746556980627022070 377
UVM_ERROR @ 2907.806520 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2907.806520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_power_glitch_reset 33405783724376722916279117586277030404809923357394582830904551783038876926798 377
UVM_ERROR @ 2925.223108 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2925.223108 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_power_glitch_reset 109156501576528691715518427093598869549459793294620677481418281605743791488886 377
UVM_ERROR @ 3378.571532 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3378.571532 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_test_status_if.sv:65) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] SW test status must not change after reaching the pass or fail state. 3 test runs
chip_sw_clkmgr_reset_frequency 105176193141082123180237514465052456275896570616689217958717191064391771686732 400
UVM_INFO @ 8269.215580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_reset_frequency 87399203381325632133594297713093491951901720984167465813765451486921392630663 400
UVM_INFO @ 8489.889352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_reset_frequency 113139486781264357610421642623739777718800071817518434193165256879831375715579 400
UVM_INFO @ 10901.361078 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_clkmgr_jitter_frequency 47209138677038209823593774393284286681800991839260019163663763318675984624211 407
UVM_INFO @ 2942.803294 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_jitter_frequency 9706987445483685896445128134264325024065180057713634166313658790039995609592 407
UVM_INFO @ 3729.951394 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_jitter_frequency 72275414951768846368694258336823381719665125234122666224027422032502958673594 407
UVM_INFO @ 3221.665705 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 3 test runs
chip_sw_ast_clk_rst_inputs 70493660393319810547206088070301748393554940587141672053617982756530800064128 391
UVM_INFO @ 12919.607400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_ast_clk_rst_inputs 115026292034192164684150306039781094454294327132233149035732216918400887147894 391
UVM_INFO @ 9125.866604 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_ast_clk_rst_inputs 34546505182461439799648849886490139204112624715203163098721837712005980176079 391
UVM_INFO @ 9197.715063 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 3 test runs
ate_bootstrap_flash_erase 34990120406394427616209032874782468098131535155655983318461870144299407778508 339
UVM_INFO @ 10010.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ate_bootstrap_flash_erase 36010050122997563315849183477826244281048140860349801648590203271892262089024 339
UVM_INFO @ 10010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ate_bootstrap_flash_erase 31471489855731773912929273670297202699396085036546607454143948132781572190234 339
UVM_INFO @ 10010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:604) [debugger] Check failed pc == exp_addr (* [*] vs * [*]) 3 test runs
rom_e2e_jtag_debug_test_unlocked0 32128394245119258940506753887706297601663257393927984850232600320857772398315 359
UVM_INFO @ 2072.481000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_jtag_debug_dev 15384388182690979752609321501471036190954183409755220708769863973205852676646 359
UVM_INFO @ 2202.908500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_jtag_debug_rma 3490132146927883977528278432969363144216641718148827182004417150409673570211 359
UVM_INFO @ 1696.532500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:1072)] Unexpected fault 3 test runs
chip_sw_all_escalation_resets 62855488024399325779194428883626854165033974441546388948709386828642046646438 375
UVM_INFO @ 3465.241440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 69765084418966615124505751529787336839952099279290393788631025517575286551583 375
UVM_INFO @ 2658.789240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 101912159911030985519005206942625121113447615455317777105200553064235898833980 375
UVM_INFO @ 3355.808370 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:887) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl 2 test runs
chip_sw_lc_ctrl_test_locked0_to_scrap 102998562918424545294523843744119158742122877209543238406622997793357380596331 375
UVM_INFO @ 8275.319965 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_ctrl_rand_to_scrap 38315968147227968057794468218268967972812205091320436751272912784822324683172 375
UVM_INFO @ 10919.279352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:340) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 2 test runs
chip_sw_hmac_multistream 108893977112406312588064226006589671879516108744942077880328151487596256712538 438
UVM_INFO @ 12010.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_hmac_multistream 1677185280684821971639720990211974090856346363220530469672805394459060366763 417
UVM_INFO @ 12010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_riscv_driver.sv:208) driver [driver] Could not activate RV_DM after * attempts! 2 test runs
chip_jtag_csr_rw 13329131707569199205027097571423284481783749008310239538670846379564402212159 5365
UVM_INFO @ 2453.262155 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_jtag_csr_rw 115196616460107493524577012923565796652239461258620065580487835440953470666107 5365
UVM_INFO @ 2107.351688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 2 test runs
chip_rv_dm_lc_disabled 57501030506515253521433000633486987876412672159770260598118646527940283552856 306
UVM_INFO @ 4164.652635 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_rv_dm_lc_disabled 49020886838813451771273743356832628827650536987058313561393520048398821159015 292
UVM_INFO @ 1979.486206 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:614)] CHECK-fail: Unexpected mtval: expected *, got * 2 test runs
chip_sw_all_escalation_resets 34162778549528900812223434192661904294042837917777100791560860223338349019906 383
UVM_INFO @ 3014.636520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 40047204399286878079635009950800108581762659792400391573708436682575045507203 383
UVM_INFO @ 3333.006825 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(pin_wkup_req_o))' 1 test run
chip_sw_sleep_pin_wake 78703240892797120515659424752687840664010799053198372612252652557127137816068 382
UVM_ERROR @ 2907.158000 us: (pinmux.sv:662) [ASSERT FAILED] AonWkupReqKnownO_A
UVM_INFO @ 2907.158000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:550)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 26737069733860727553371092849490328210310134476998856048216749688154741037393 371
UVM_INFO @ 2772.364997 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_rv_dm_lc_disabled_vseq.sv:154) [chip_rv_dm_lc_disabled_vseq] Check failed rdata == exp_data (* [*] vs * [*]) RV_DM sbaddress* read back check failed, got *, expected * 1 test run
chip_rv_dm_lc_disabled 39522241646485607056482137695475307880179074782029398076997008483908930771626 292
UVM_INFO @ 1578.363522 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:711) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 1 test run
chip_csr_mem_rw_with_rand_reset 115516967111396483834348888708438660483614800849238802985200458502685679133221 288
TL item was: req: (cip_tl_seq_item@37430) { a_addr: 'h11000000 a_data: 'h6cf81162 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2 a_opcode: 'h0 a_user: 'h25e87 d_param: 'h0 d_source: 'h2 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 1672.844935 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:923) virtual_sequencer [chip_sw_lc_walkthrough_testunlocks_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_walkthrough_testunlocks 20692060361578296504688230271472975667900091503003261882902040412298676410284 405
UVM_INFO @ 36277.587852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:370)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 37087463261982431318510388852744249055469555683186213942639405740352221026367 371
UVM_INFO @ 3002.746725 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_lc_raw_unlock_vseq.sv:57) [chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement 1 test run
rom_raw_unlock 28281012034715214830166952302328248846561890411417808318263724996858361353475 398
UVM_INFO @ 22052.127678 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:340)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 30040172896889386388789116535665831870264407049361593694626353869395281460757 371
UVM_INFO @ 3165.206774 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rv_jtag_o == '0)' 1 test run
chip_sw_rv_dm_access_after_escalation_reset 18442561557072124160715753198158147102068075532544852895319225531036239923109 387
UVM_ERROR @ 3036.712152 us: (pinmux_strap_sampling.sv:516) [ASSERT FAILED] RvTapOff1_A
UVM_INFO @ 3036.712152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: chip_reg_block.pinmux.mio_pad_sleep_mode_* reset value: * 1 test run
chip_csr_mem_rw_with_rand_reset 7815433258321522023339832232848141911300581105969081721578189138403070737024 296
UVM_INFO @ 4806.600584 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---