| V1 |
|
100.00% |
| V2 |
|
85.63% |
| V2S |
|
96.67% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 10 | 10 | 100.00 | |||
| sysrst_ctrl_smoke | 8.010s | 2110.333us | 10 | 10 | 100.00 | |
| input_output_inverted | 10 | 10 | 100.00 | |||
| sysrst_ctrl_in_out_inverted | 9.490s | 2479.121us | 10 | 10 | 100.00 | |
| combo_detect_ec_rst | 5 | 5 | 100.00 | |||
| sysrst_ctrl_combo_detect_ec_rst | 9.460s | 2406.549us | 5 | 5 | 100.00 | |
| combo_detect_ec_rst_with_pre_cond | 5 | 5 | 100.00 | |||
| sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | 9.630s | 2316.443us | 5 | 5 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sysrst_ctrl_csr_hw_reset | 5.510s | 6091.022us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| sysrst_ctrl_csr_rw | 7.900s | 2033.280us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sysrst_ctrl_csr_bit_bash | 33.330s | 71832.224us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sysrst_ctrl_csr_aliasing | 8.210s | 2135.714us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| sysrst_ctrl_csr_mem_rw_with_rand_reset | 8.440s | 2079.037us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| sysrst_ctrl_csr_rw | 7.900s | 2033.280us | 5 | 5 | 100.00 | |
| sysrst_ctrl_csr_aliasing | 8.210s | 2135.714us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| combo_detect | 25 | 25 | 100.00 | |||
| sysrst_ctrl_combo_detect | 327.540s | 101662.958us | 25 | 25 | 100.00 | |
| combo_detect_with_pre_cond | 92 | 100 | 92.00 | |||
| sysrst_ctrl_combo_detect_with_pre_cond | 495.120s | 162893.345us | 92 | 100 | 92.00 | |
| auto_block_key_outputs | 25 | 25 | 100.00 | |||
| sysrst_ctrl_auto_blk_key_output | 868.780s | 285196.612us | 25 | 25 | 100.00 | |
| keyboard_input_triggered_interrupt | 35 | 50 | 70.00 | |||
| sysrst_ctrl_edge_detect | 1405.100s | 488455.004us | 35 | 50 | 70.00 | |
| pin_output_keyboard_inversion_control | 10 | 10 | 100.00 | |||
| sysrst_ctrl_pin_override_test | 9.840s | 2512.152us | 10 | 10 | 100.00 | |
| pin_input_value_accessibility | 10 | 10 | 100.00 | |||
| sysrst_ctrl_pin_access_test | 8.510s | 2035.698us | 10 | 10 | 100.00 | |
| ec_power_on_reset | 10 | 10 | 100.00 | |||
| sysrst_ctrl_ec_pwr_on_rst | 12.950s | 3742.058us | 10 | 10 | 100.00 | |
| flash_write_protect_output | 10 | 10 | 100.00 | |||
| sysrst_ctrl_flash_wr_prot_out | 9.650s | 2612.802us | 10 | 10 | 100.00 | |
| ultra_low_power_test | 3 | 25 | 12.00 | |||
| sysrst_ctrl_ultra_low_pwr | 9.660s | 4178.842us | 3 | 25 | 12.00 | |
| sysrst_ctrl_feature_disable | 2 | 2 | 100.00 | |||
| sysrst_ctrl_feature_disable | 58.590s | 38437.006us | 2 | 2 | 100.00 | |
| stress_all | 7 | 10 | 70.00 | |||
| sysrst_ctrl_stress_all | 202.230s | 268038.727us | 7 | 10 | 70.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| sysrst_ctrl_alert_test | 7.880s | 2012.814us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| sysrst_ctrl_intr_test | 8.080s | 2013.616us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| sysrst_ctrl_tl_errors | 9.800s | 2149.972us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| sysrst_ctrl_tl_errors | 9.800s | 2149.972us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| sysrst_ctrl_csr_hw_reset | 5.510s | 6091.022us | 1 | 1 | 100.00 | |
| sysrst_ctrl_csr_rw | 7.900s | 2033.280us | 5 | 5 | 100.00 | |
| sysrst_ctrl_csr_aliasing | 8.210s | 2135.714us | 1 | 1 | 100.00 | |
| sysrst_ctrl_same_csr_outstanding | 23.450s | 4891.257us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| sysrst_ctrl_csr_hw_reset | 5.510s | 6091.022us | 1 | 1 | 100.00 | |
| sysrst_ctrl_csr_rw | 7.900s | 2033.280us | 5 | 5 | 100.00 | |
| sysrst_ctrl_csr_aliasing | 8.210s | 2135.714us | 1 | 1 | 100.00 | |
| sysrst_ctrl_same_csr_outstanding | 23.450s | 4891.257us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 29 | 30 | 96.67 | |||
| sysrst_ctrl_sec_cm | 133.200s | 42010.863us | 4 | 5 | 80.00 | |
| sysrst_ctrl_tl_intg_err | 108.350s | 42409.710us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| sysrst_ctrl_tl_intg_err | 108.350s | 42409.710us | 25 | 25 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 10 | 10 | 100.00 | |||
| sysrst_ctrl_stress_all_with_rand_reset | 22.380s | 6577.989us | 10 | 10 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error | 36 test runs | |||
| sysrst_ctrl_edge_detect | 32582451012597799899664457478082374778909662928407868944442059529350737494775 | 670 |
UVM_ERROR @ 4999174045 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 4999174045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_ultra_low_pwr | 100277061935162485728308865578373394593479718308648157063317805165669184212563 | 661 |
UVM_ERROR @ 5614069687 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 5614069687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_stress_all | 8011547460940473093954605193690603791867898714505245599262572196644788659554 | 663 |
UVM_ERROR @ 412299164159 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 412299164159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_stress_all | 67711752742140442079047061054249546153165337083409630668990343212996689539997 | 662 |
UVM_ERROR @ 5645501266 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 5645501266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_ultra_low_pwr | 61990969031017351486329651775714515168274998022426723657920940083894496434526 | 662 |
UVM_ERROR @ 3723185828 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 3723185828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_ultra_low_pwr | 82628995766021140890267654207577658583246063850920373961914242648218178153108 | 662 |
UVM_ERROR @ 266270488689 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 266270488689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_ultra_low_pwr | 19080547599565164759104868479753171970269258297018890286991255871735534076470 | 662 |
UVM_ERROR @ 4138028482 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 4138028482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_edge_detect | 27075928732319531125581334111553276847476006399192195081967742003998477224968 | 672 |
UVM_ERROR @ 3883852920 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 3883852920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_stress_all | 54407346156065168512381950338571007275649121019402853312378547773188234393357 | 662 |
UVM_ERROR @ 9018291295 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 9018291295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_ultra_low_pwr | 35407969043020998001877963563043722596007430874773011845682588058790923978006 | 663 |
UVM_ERROR @ 5524903921 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 5524903921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_ultra_low_pwr | 87378228485590402947791243669496484955763575623837601278835973940526020543920 | 662 |
UVM_ERROR @ 3064689493 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 3064689493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_ultra_low_pwr | 7044909884861454891555702865011183704637498962640624757394919538759488617594 | 661 |
UVM_ERROR @ 4155958805 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 4155958805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_ultra_low_pwr | 48740347367190983154354296543912430397611631930470251561985456804149868291557 | 661 |
UVM_ERROR @ 6056743184 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 6056743184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_edge_detect | 85541705264937237826806910494980607387883027795149972782788351257330758894974 | 667 |
UVM_ERROR @ 265809634547 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 265809634547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_ultra_low_pwr | 102659366837520339583703099843103957877180780613055918008785103536518833098943 | 662 |
UVM_ERROR @ 2563512569 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 2563512569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_ultra_low_pwr | 42254838955560131804347382851312087357561376580032741159629878110992696418360 | 661 |
UVM_ERROR @ 3258970547 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 3258970547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_edge_detect | 30361399244993440118335382748388567427777719957409100482178645949980156805168 | 668 |
UVM_ERROR @ 4198397723 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 4198397723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_ultra_low_pwr | 89952938158438436271940688915042834829194292028577802290938544929171518085332 | 662 |
UVM_ERROR @ 4178841898 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 4178841898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_ultra_low_pwr | 70659865493825253538227022661972958199930678993621370411968828592852217568808 | 662 |
UVM_ERROR @ 3814114527 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 3814114527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_edge_detect | 94717998844818656839401411346594756632840204093123954053745470639911205315766 | 670 |
UVM_ERROR @ 2663548477 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 2663548477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_ultra_low_pwr | 59731471718554932378607835148779375357183995136143891485266558886583131557086 | 661 |
UVM_ERROR @ 2648466814 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 2648466814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_ultra_low_pwr | 86461458535723202448131981540909338876302106051610270628423187178992033734837 | 662 |
UVM_ERROR @ 4925031809 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 4925031809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_ultra_low_pwr | 33736022459297062906664884001419859492997112454294127475417430078661104813472 | 661 |
UVM_ERROR @ 3820993440 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 3820993440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_edge_detect | 108937870653259482042675704159235815758123182538671673796056006738787170994504 | 666 |
UVM_ERROR @ 2335239159 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 2335239159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_ultra_low_pwr | 109974311830138032542902900784701069080244311343831174985256198357945080497951 | 661 |
UVM_ERROR @ 2698052326 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 2698052326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_edge_detect | 104920726710560339265102861249610448032581968911161150880758387904930574210173 | 664 |
UVM_ERROR @ 2645326386 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 2645326386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_ultra_low_pwr | 105649609462106364794109580537450693977051440236938233051108741841155216369605 | 661 |
UVM_ERROR @ 5872719587 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 5872719587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_ultra_low_pwr | 98236865226091304246185922000537146675814055522638410179049391364858837452976 | 661 |
UVM_ERROR @ 3851836426 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 3851836426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_edge_detect | 41060744140143936065453655162404328776581332706821025417316670038955718679142 | 663 |
UVM_ERROR @ 138128219871 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 138128219871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_edge_detect | 54391393258631163142016366793010917758172138674577813382010958773793528602469 | 680 |
UVM_ERROR @ 5526527164 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 5526527164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_edge_detect | 11617486005191188827822626016449787673527844347562142526672248863821701014770 | 664 |
UVM_ERROR @ 3069363184 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 3069363184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_edge_detect | 81183260325530306364253026585726554170651476883209205023604245095094859976471 | 670 |
UVM_ERROR @ 2937590438 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 2937590438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_edge_detect | 42560717685675680812918536464975786104113782804976370352268313961590457017113 | 667 |
UVM_ERROR @ 3074097551 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 3074097551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sysrst_ctrl_edge_detect | 581730297219438152698480232382277147832085592838008347326233075196969661193 | 668 |
UVM_ERROR @ 2681572658 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 2681572658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| sysrst_ctrl_edge_detect | 105115143482377232557004398086173624229526235993419897788963767382541630254631 | 665 |
UVM_ERROR @ 2964499685 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 2964499685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| sysrst_ctrl_edge_detect | 14731142382791991226063242948324260474138309145801587099817947889345059183157 | 689 |
UVM_ERROR @ 4918032644 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 4918032644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) | 4 test runs | |||
| sysrst_ctrl_ultra_low_pwr | 91752229307290806166242877928392306823005121395745297924108989745178630296941 | 661 |
UVM_ERROR @ 3495062437 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 3495062437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| sysrst_ctrl_ultra_low_pwr | 8181370712855311177104511487951858159707567587825220564136786161593766119702 | 661 |
UVM_ERROR @ 4711410920 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 4711410920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| sysrst_ctrl_ultra_low_pwr | 46585807814141784990537542869954186664244920624458726450386154588806731852552 | 661 |
UVM_INFO @ 2571181381 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
UVM_ERROR @ 4156507905 ps: (cip_base_scoreboard.sv:256) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 4156507905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| sysrst_ctrl_ultra_low_pwr | 49965418780260804690756435423444891885277038158681197015287858286677859773990 | 661 |
UVM_ERROR @ 5171831101 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 5171831101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) | 2 test runs | |||
| sysrst_ctrl_combo_detect_with_pre_cond | 58656971322771614992128436181524423510539038902878141395614699937947609925424 | 671 |
UVM_ERROR @ 13525283380 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 13525283380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| sysrst_ctrl_combo_detect_with_pre_cond | 3790906758820066697813473797120420559225453840209120709511087186870397272114 | 676 |
UVM_ERROR @ 25523467449 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 25523467449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(8) vs exp(3) +/-* | 2 test runs | |||
| sysrst_ctrl_combo_detect_with_pre_cond | 69284831679855084967502457038553854415036351405498189240354085472412092868064 | 680 |
UVM_ERROR @ 34034015893 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(8) vs exp(3) +/-4
UVM_INFO @ 34034015893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| sysrst_ctrl_combo_detect_with_pre_cond | 115317855514493296735780516075915901010771951270892442002556220728104801955763 | 669 |
UVM_ERROR @ 13050096539 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(8) vs exp(3) +/-4
UVM_INFO @ 13050096539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [sysrst_ctrl_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. | 1 test run | |||
| sysrst_ctrl_sec_cm | 101758565308565091446532746165878228578563133981516967259914911279128592135708 | 698 |
UVM_INFO @ 23999423415 ps: (cip_base_vseq__sec_cm_fi.svh:8) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_sec_cm_fi_vseq 12/20
UVM_INFO @ 23999428415 ps: (prim_onehot_check_if.sv:103) [tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if.\prim_onehot_check_if_proxy::inject_fault ] onehot_fault_type: OnehotFault
UVM_INFO @ 23999428415 ps: (prim_onehot_check_if.sv:107) [tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if.\prim_onehot_check_if_proxy::inject_fault ] Forcing tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.en_i from 0 to 0, tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.oh_i from 0 to 2708138614799 and tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.addr_i from 0 to 27
UVM_INFO @ 25999423415 ps: (cip_base_vseq__sec_cm_fi.svh:8) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_sec_cm_fi_vseq 13/20
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| UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(2) +/-* | 1 test run | |||
| sysrst_ctrl_combo_detect_with_pre_cond | 26534425866309048413938235928183273779734331426796421720406144363447688415029 | 674 |
UVM_INFO @ 14250981454 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:152) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_h2l_expected == 0
UVM_INFO @ 14480981454 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 14500981454 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 24578585063 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x32
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| UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) | 1 test run | |||
| sysrst_ctrl_combo_detect_with_pre_cond | 33569831947270182209338661130902385397209016417943627296274573422822310842841 | 674 |
UVM_INFO @ 15744980630 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 15764980630 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 25975636076 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2d
UVM_INFO @ 25975667327 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x2b
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| UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*]) | 1 test run | |||
| sysrst_ctrl_combo_detect_with_pre_cond | 9272741925791678457991698026853635653744912516438878350278969268599047593155 | 683 |
UVM_ERROR @ 32673186821 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 8 [0x8])
UVM_INFO @ 32673186821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(6) vs exp(2) +/-* | 1 test run | |||
| sysrst_ctrl_combo_detect_with_pre_cond | 40276828212474452176558291546456420188369565279862006254849854519392596908033 | 669 |
UVM_ERROR @ 15073123644 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(6) vs exp(2) +/-4
UVM_INFO @ 15073123644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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