Simulation Results

Simulation Results: sysrst_ctrl

12/09/2026 09:15:14 DVSim: v1.49.0 sha: fca045d json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
94.34 %

code
98.37 %

assert
98.86 %

func
85.79 %

line
99.35 %

branch
99.33 %

cond
97.65 %

toggle
100.00 %

FSM
95.51 %

Validation stages

V1		100.00%
V2		85.03%
V2S		93.33%
V3		100.00%

43/43 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	sysrst_ctrl_smoke	8.830s	2111.919us	10	10	100.00
input_output_inverted				10	10	100.00
	sysrst_ctrl_in_out_inverted	10.490s	2471.233us	10	10	100.00
combo_detect_ec_rst				5	5	100.00
	sysrst_ctrl_combo_detect_ec_rst	7.400s	2402.291us	5	5	100.00
combo_detect_ec_rst_with_pre_cond				5	5	100.00
	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	7.680s	2307.307us	5	5	100.00
csr_hw_reset				1	1	100.00
	sysrst_ctrl_csr_hw_reset	8.710s	6055.653us	1	1	100.00
csr_rw				5	5	100.00
	sysrst_ctrl_csr_rw	7.840s	2032.540us	5	5	100.00
csr_bit_bash				1	1	100.00
	sysrst_ctrl_csr_bit_bash	52.240s	76239.218us	1	1	100.00
csr_aliasing				1	1	100.00
	sysrst_ctrl_csr_aliasing	3.090s	2220.156us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	sysrst_ctrl_csr_mem_rw_with_rand_reset	7.450s	2067.950us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	sysrst_ctrl_csr_rw	7.840s	2032.540us	5	5	100.00
	sysrst_ctrl_csr_aliasing	3.090s	2220.156us	1	1	100.00

284/334 passed

85.03 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
combo_detect				25	25	100.00
	sysrst_ctrl_combo_detect	495.450s	185456.248us	25	25	100.00
combo_detect_with_pre_cond				95	100	95.00
	sysrst_ctrl_combo_detect_with_pre_cond	500.110s	200878.062us	95	100	95.00
auto_block_key_outputs				25	25	100.00
	sysrst_ctrl_auto_blk_key_output	581.460s	210246.977us	25	25	100.00
keyboard_input_triggered_interrupt				30	50	60.00
	sysrst_ctrl_edge_detect	567.320s	480958.401us	30	50	60.00
pin_output_keyboard_inversion_control				10	10	100.00
	sysrst_ctrl_pin_override_test	9.660s	2508.615us	10	10	100.00
pin_input_value_accessibility				10	10	100.00
	sysrst_ctrl_pin_access_test	7.690s	2165.539us	10	10	100.00
ec_power_on_reset				10	10	100.00
	sysrst_ctrl_ec_pwr_on_rst	1284.550s	555500.512us	10	10	100.00
flash_write_protect_output				10	10	100.00
	sysrst_ctrl_flash_wr_prot_out	10.690s	2611.414us	10	10	100.00
ultra_low_power_test				4	25	16.00
	sysrst_ctrl_ultra_low_pwr	176.160s	1535340.178us	4	25	16.00
sysrst_ctrl_feature_disable				2	2	100.00
	sysrst_ctrl_feature_disable	67.000s	32402.508us	2	2	100.00
stress_all				6	10	60.00
	sysrst_ctrl_stress_all	479.080s	186824.326us	6	10	60.00
alert_test				10	10	100.00
	sysrst_ctrl_alert_test	8.200s	2012.334us	10	10	100.00
intr_test				10	10	100.00
	sysrst_ctrl_intr_test	8.430s	2012.260us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	sysrst_ctrl_tl_errors	9.330s	2062.809us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	sysrst_ctrl_tl_errors	9.330s	2062.809us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	sysrst_ctrl_csr_hw_reset	8.710s	6055.653us	1	1	100.00
	sysrst_ctrl_csr_rw	7.840s	2032.540us	5	5	100.00
	sysrst_ctrl_csr_aliasing	3.090s	2220.156us	1	1	100.00
	sysrst_ctrl_same_csr_outstanding	19.460s	7078.233us	5	5	100.00
tl_d_partial_access				12	12	100.00
	sysrst_ctrl_csr_hw_reset	8.710s	6055.653us	1	1	100.00
	sysrst_ctrl_csr_rw	7.840s	2032.540us	5	5	100.00
	sysrst_ctrl_csr_aliasing	3.090s	2220.156us	1	1	100.00
	sysrst_ctrl_same_csr_outstanding	19.460s	7078.233us	5	5	100.00

V2S

28/30 passed

93.33 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				28	30	93.33
	sysrst_ctrl_sec_cm	101.340s	42044.029us	5	5	100.00
	sysrst_ctrl_tl_intg_err	111.470s	42399.229us	23	25	92.00
sec_cm_bus_integrity				23	25	92.00
	sysrst_ctrl_tl_intg_err	111.470s	42399.229us	23	25	92.00

10/10 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				10	10	100.00
	sysrst_ctrl_stress_all_with_rand_reset	21.080s	11540.938us	10	10	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error				44 test runs
	sysrst_ctrl_ultra_low_pwr	15005637766197199742413112200772022032219806673021378067661823664565182688852	661	UVM_ERROR @ 3730808050 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 3730808050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	30257771214700025303421380502009632969783902907686726176151317757729240551816	661	UVM_ERROR @ 1162104487236 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 1162104487236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	78662381835332111156200677893065948747823019998765560202639728316100986022687	666	UVM_ERROR @ 131673663811 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 131673663811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_stress_all	94478845390830475750403863291665976713380700063663306121995346201090216409001	662	UVM_ERROR @ 8133375192 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 8133375192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	68149762026419746348963533145880934435680289847233388167419170162154046997023	661	UVM_ERROR @ 288173902733 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 288173902733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	42417986140519104555705066927443081697385875764388732410482293757583086717200	662	UVM_ERROR @ 5786733252 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 5786733252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	74943604858940895907411191044390584074963312913235177324656051699409590262537	661	UVM_ERROR @ 4451401434 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 4451401434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	110931227661585915387970070251974948690885418480633890601473929493992159338769	662	UVM_ERROR @ 274686292268 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 274686292268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_stress_all	23979042933360754776917906374497442155935461680600275358501903824743542590047	717	UVM_ERROR @ 171186451581 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 171186451581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	104385044766451131848422077698120554324798576794621747966358497207642186358809	662	UVM_ERROR @ 3522801640 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 3522801640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_stress_all	54391860415239498090413231539231826025997780031494518530851496915294642292620	673	UVM_ERROR @ 13324492736 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 13324492736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	57177025926103128284281888640521999008065259866931660780337228498244789872317	661	UVM_ERROR @ 4688632927 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 4688632927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	41699183619248441618205835028402888396620221422907647137115840255939672808779	665	UVM_ERROR @ 2336189236 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 2336189236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	17098999072689831801190262885988115987677468989465488482737440053433292752861	662	UVM_ERROR @ 5945248516 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 5945248516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	50715360720793578104338862510345197692881967769582782111593636965490521750518	662	UVM_ERROR @ 1535340178482 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 1535340178482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	63174577431875594004245840159678810311643738971381373524756000325410025278504	688	UVM_ERROR @ 4626640721 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 4626640721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_stress_all	113440564619625765140571928204438237170254370314818163872815552429368912682642	721	UVM_ERROR @ 186824325782 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 186824325782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	19628769098319593105920259212092045329197590172090716754213773620015643583026	668	UVM_ERROR @ 2258705210 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 2258705210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	22635832571989592373771338319385340108790408004687258917313113715643303669698	662	UVM_ERROR @ 1614148896230 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 1614148896230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	76949745375203313131877562126137788367090453887455341506362049520155953525931	661	UVM_ERROR @ 63329781834 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 63329781834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	74999537861084749353909148568672987998732646000995572285376088931967951563129	662	UVM_ERROR @ 294174533772 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 294174533772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	7099900256153694835477891131043135635858897297827496213749108190307878483209	662	UVM_ERROR @ 2631393791 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 2631393791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	64925670554555677882635562597706396182820855885202285248804799108736290274542	662	UVM_ERROR @ 5598822169 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 5598822169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	38676946421059384411010200161831801326436396515708215224634140984255822144707	670	UVM_ERROR @ 2345144286 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 2345144286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	106070350675377282079915955272285943733639073851097941165633682020631540760620	661	UVM_ERROR @ 2824071179 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 2824071179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	108827100267568333892031439815962718580612609908431986127661848609382791649436	664	UVM_ERROR @ 2572071390 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 2572071390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	33116314298786964030373952387297282255667543378982407217552077991147205569691	661	UVM_ERROR @ 4023420460 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 4023420460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	31727339478168919019019685376441157276950729995482547952756942232030824573367	661	UVM_ERROR @ 4083075941 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 4083075941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	53638284432424223296927123342828688149465107017910165561988562183160674062846	662	UVM_ERROR @ 3222409582 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 3222409582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	41119709332012749242252345502337136334737853561538122755185592434863248868257	661	UVM_ERROR @ 3948445185 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 3948445185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	7285071804432871682577032084111873904641045213602207237706715011432087116862	667	UVM_ERROR @ 2696595972 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 2696595972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	50483613960674380185346038703237166498373912635216500977647910654283948019615	662	UVM_ERROR @ 3269782246 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 3269782246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	50492911405450378603484715816765782753437025105357966907780134050194745520587	668	UVM_ERROR @ 3322070800 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 3322070800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	17251174408436458693090722133478896171291823822031215595993281831705359893437	662	UVM_ERROR @ 2819591865 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 2819591865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	101940285372725851137068758963904559274564762438867015936619438650268656178896	662	UVM_ERROR @ 5976194893 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 5976194893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	108603809085300442332707130991222934229084084679055104106334415569590076131047	663	UVM_ERROR @ 2324982895 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 2324982895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	15417780123815808765240436584797129575403672844259524276665522288877219484448	663	UVM_ERROR @ 2663280859 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 2663280859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	66748375452741723809698213151371616554373930182051782864753687297414235160526	670	UVM_ERROR @ 600418349338 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 600418349338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	23808147541175805271462678004763137158862009828750056370205714210123307003848	669	UVM_ERROR @ 480958401126 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 480958401126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	56054766897013111891187798274146597290277597163118038861730071544486173048391	671	UVM_ERROR @ 4306882015 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 4306882015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	111805841421237860555410381811988552183824769491582198143124293114188017281748	666	UVM_ERROR @ 2259534598 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 2259534598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	95974723421194769030165930193193875899247643061188528414027745005341184872345	664	UVM_ERROR @ 2923942505 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 2923942505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	78088946775088963692845008662094436827604900308390693834728084909568012357046	668	UVM_ERROR @ 2756950217 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 2756950217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	78924000111034408677382562797089456849061858154578269926241480100634973762176	667	UVM_ERROR @ 2417704579 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 2417704579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [] vs [*])				2 test runs
	sysrst_ctrl_combo_detect_with_pre_cond	39344087478222057957707812497988456734936953266486238856812635536491234288322	691	UVM_ERROR @ 44131634522 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 44131634522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_combo_detect_with_pre_cond	85918652035473376040345216856806971107163768372632750963145836099116569716181	711	UVM_INFO @ 64623594221 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2d UVM_INFO @ 64623656720 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x25 UVM_INFO @ 65127288163 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0 UVM_INFO @ 65127288163 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 1
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [sysrst_ctrl_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.				2 test runs
	sysrst_ctrl_tl_intg_err	82117303213284967128409741172737254722551988227390399033053348938574624318682	672	UVM_INFO @ 6040453421 ps: (cip_base_vseq__tl_errors.svh:409) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_tl_intg_err_vseq 3/10 UVM_INFO @ 6060547555 ps: (cip_tl_seq_item.sv:117) uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq.tl_seq.req] TL data or integrity bits have been flipped, see the changes as below: a_addr: 0x445cd074 -> 0x444c5074 a_opcode: 0x4
	sysrst_ctrl_tl_intg_err	42170614417079185698336583758367066423713537791425873511972586931655959489046	731	UVM_INFO @ 18334686619 ps: (cip_base_vseq__tl_errors.svh:409) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_tl_intg_err_vseq 9/10 UVM_INFO @ 18348020059 ps: (cip_tl_seq_item.sv:132) uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq.tl_seq.req] TL data or integrity bits have been flipped, see the changes as below: a_data: 0x381937a6 -> 0xb89937a6
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(10) vs exp(5) +/-*				1 test run
	sysrst_ctrl_combo_detect_with_pre_cond	25257956779307126912308220400244319652280063932414020619496289903913794477716	677	UVM_ERROR @ 27066444300 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(10) vs exp(5) +/-4 UVM_INFO @ 27066444300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)				1 test run
	sysrst_ctrl_ultra_low_pwr	68834280606330269372894116813879474897137432185331074617154088860485984276027	661	UVM_INFO @ 2364611692 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i UVM_ERROR @ 3865262049 ps: (cip_base_scoreboard.sv:256) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_INFO @ 3865262049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:111) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_l2h_expected == *) Unexpected L2H transition of ec_rst_l_o				1 test run
	sysrst_ctrl_combo_detect_with_pre_cond	62242387952283516978584788923426388520495820828752879494453730376218980103984	732	UVM_INFO @ 63382284687 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1 UVM_INFO @ 63402284687 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0 UVM_INFO @ 73538563854 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x31 UVM_INFO @ 73538625078 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x17
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(10) vs exp(5) +/-*				1 test run
	sysrst_ctrl_combo_detect_with_pre_cond	98897853887759673811526702300821353632589289547096820984004626880775403766052	716	UVM_INFO @ 69457619512 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1 UVM_INFO @ 69477619512 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0 UVM_INFO @ 79539611856 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2a UVM_INFO @ 79539753270 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x32