Simulation Results

Simulation Results: sysrst_ctrl

19/09/2026 01:30:47 DVSim: v1.49.0 sha: 66cdfd3 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
94.79 %

code
98.57 %

assert
98.96 %

func
86.85 %

line
99.50 %

branch
99.59 %

cond
97.63 %

toggle
100.00 %

FSM
96.15 %

Validation stages

V1		100.00%
V2		97.31%
V2S		93.33%
V3		100.00%

43/43 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	sysrst_ctrl_smoke	7.020s	2109.126us	10	10	100.00
input_output_inverted				10	10	100.00
	sysrst_ctrl_in_out_inverted	9.530s	2474.018us	10	10	100.00
combo_detect_ec_rst				5	5	100.00
	sysrst_ctrl_combo_detect_ec_rst	8.280s	2420.120us	5	5	100.00
combo_detect_ec_rst_with_pre_cond				5	5	100.00
	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	5.180s	2551.841us	5	5	100.00
csr_hw_reset				1	1	100.00
	sysrst_ctrl_csr_hw_reset	4.810s	4053.163us	1	1	100.00
csr_rw				5	5	100.00
	sysrst_ctrl_csr_rw	8.640s	2037.632us	5	5	100.00
csr_bit_bash				1	1	100.00
	sysrst_ctrl_csr_bit_bash	55.730s	76273.068us	1	1	100.00
csr_aliasing				1	1	100.00
	sysrst_ctrl_csr_aliasing	7.150s	2103.894us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	sysrst_ctrl_csr_mem_rw_with_rand_reset	9.130s	2088.770us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	sysrst_ctrl_csr_rw	8.640s	2037.632us	5	5	100.00
	sysrst_ctrl_csr_aliasing	7.150s	2103.894us	1	1	100.00

325/334 passed

97.31 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
combo_detect				25	25	100.00
	sysrst_ctrl_combo_detect	427.250s	187477.562us	25	25	100.00
combo_detect_with_pre_cond				93	100	93.00
	sysrst_ctrl_combo_detect_with_pre_cond	378.140s	151400.369us	93	100	93.00
auto_block_key_outputs				25	25	100.00
	sysrst_ctrl_auto_blk_key_output	453.620s	228270.174us	25	25	100.00
keyboard_input_triggered_interrupt				50	50	100.00
	sysrst_ctrl_edge_detect	578.140s	537094.189us	50	50	100.00
pin_output_keyboard_inversion_control				10	10	100.00
	sysrst_ctrl_pin_override_test	9.050s	2510.465us	10	10	100.00
pin_input_value_accessibility				10	10	100.00
	sysrst_ctrl_pin_access_test	8.960s	2137.883us	10	10	100.00
ec_power_on_reset				9	10	90.00
	sysrst_ctrl_ec_pwr_on_rst	751.970s	702421.548us	9	10	90.00
flash_write_protect_output				10	10	100.00
	sysrst_ctrl_flash_wr_prot_out	8.940s	2610.167us	10	10	100.00
ultra_low_power_test				24	25	96.00
	sysrst_ctrl_ultra_low_pwr	20.200s	78529.880us	24	25	96.00
sysrst_ctrl_feature_disable				2	2	100.00
	sysrst_ctrl_feature_disable	93.200s	35790.586us	2	2	100.00
stress_all				10	10	100.00
	sysrst_ctrl_stress_all	248.880s	72169.344us	10	10	100.00
alert_test				10	10	100.00
	sysrst_ctrl_alert_test	7.350s	2013.541us	10	10	100.00
intr_test				10	10	100.00
	sysrst_ctrl_intr_test	7.930s	2011.925us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	sysrst_ctrl_tl_errors	9.610s	2042.572us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	sysrst_ctrl_tl_errors	9.610s	2042.572us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	sysrst_ctrl_csr_hw_reset	4.810s	4053.163us	1	1	100.00
	sysrst_ctrl_csr_rw	8.640s	2037.632us	5	5	100.00
	sysrst_ctrl_csr_aliasing	7.150s	2103.894us	1	1	100.00
	sysrst_ctrl_same_csr_outstanding	31.520s	8177.604us	5	5	100.00
tl_d_partial_access				12	12	100.00
	sysrst_ctrl_csr_hw_reset	4.810s	4053.163us	1	1	100.00
	sysrst_ctrl_csr_rw	8.640s	2037.632us	5	5	100.00
	sysrst_ctrl_csr_aliasing	7.150s	2103.894us	1	1	100.00
	sysrst_ctrl_same_csr_outstanding	31.520s	8177.604us	5	5	100.00

V2S

28/30 passed

93.33 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				28	30	93.33
	sysrst_ctrl_sec_cm	92.580s	42011.305us	4	5	80.00
	sysrst_ctrl_tl_intg_err	115.490s	42480.762us	24	25	96.00
sec_cm_bus_integrity				24	25	96.00
	sysrst_ctrl_tl_intg_err	115.490s	42480.762us	24	25	96.00

10/10 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				10	10	100.00
	sysrst_ctrl_stress_all_with_rand_reset	20.080s	6064.414us	10	10	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [sysrst_ctrl_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.				2 test runs
	sysrst_ctrl_sec_cm	11066575364625768941005445679495239283363651111666100459237756258371670549775	671	UVM_INFO @ 8001724651 ps: (cip_base_vseq__sec_cm_fi.svh:8) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_sec_cm_fi_vseq 4/20 UVM_INFO @ 8001729651 ps: (prim_onehot_check_if.sv:103) [tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if.\prim_onehot_check_if_proxy::inject_fault ] onehot_fault_type: OnehotEnableFault UVM_INFO @ 8001729651 ps: (prim_onehot_check_if.sv:107) [tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if.\prim_onehot_check_if_proxy::inject_fault ] Forcing tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.en_i from 0 to 0, tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.oh_i from 0 to 2097152 and tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.addr_i from 0 to 1 UVM_INFO @ 8001739651 ps: (prim_onehot_check_if.sv:124) [tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if.\prim_onehot_check_if_proxy::restore_fault ] Restoring original value of tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.en_i (0), tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.oh_i (0) and tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.addr_i (0)
	sysrst_ctrl_tl_intg_err	18260327183356638761437766555983023078898820275600703526325891542771905076204	824	UVM_INFO @ 42508592994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [] vs [*])				2 test runs
	sysrst_ctrl_combo_detect_with_pre_cond	55923367003107363612042538520411966127008372597103271879185670282867170181272	721	UVM_ERROR @ 61610170203 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 61610170203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_combo_detect_with_pre_cond	74033244904905711255443405972652931106736505211220479367736380175563152416159	684	UVM_ERROR @ 25466411861 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 25466411861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:111) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_l2h_expected == *) Unexpected L2H transition of ec_rst_l_o				2 test runs
	sysrst_ctrl_combo_detect_with_pre_cond	111053630075949352573839928942489482303760529884218004840189565049434064307931	771	UVM_INFO @ 97439092723 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1 UVM_INFO @ 97459092723 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0 UVM_INFO @ 107521703463 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x19 UVM_INFO @ 107521828464 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0xd
	sysrst_ctrl_combo_detect_with_pre_cond	5008799035346167634083805378719259619362043624551158444897356766251428553559	679	UVM_ERROR @ 14732527548 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_h2l_expected == 1) Unexpected H2L transition of ec_rst_l_o UVM_INFO @ 14732527548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)				1 test run
	sysrst_ctrl_ultra_low_pwr	4435149198056572177236087645212072746184822463141912174149674109105718447351	661	UVM_INFO @ 2436878834 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i UVM_INFO @ 7641878834 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check UVM_INFO @ 7655245971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == *				1 test run
	sysrst_ctrl_ec_pwr_on_rst	56077792150881796775046021569877347625758826625165068235297267516153897688499	661	UVM_INFO @ 2945416039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [] vs [*])				1 test run
	sysrst_ctrl_combo_detect_with_pre_cond	55537908126320061971201736256588263487786206892173011483516605627516785518899	679	UVM_INFO @ 30140534810 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0xc9 UVM_INFO @ 30140631584 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x29 UVM_INFO @ 30543520880 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0 UVM_INFO @ 30543520880 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 1
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(6) vs exp(2) +/-*				1 test run
	sysrst_ctrl_combo_detect_with_pre_cond	42638891743460042575196984899943584381433831669416789120107180773078837963125	672	UVM_ERROR @ 14106686778 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(6) vs exp(2) +/-4 UVM_INFO @ 14106686778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(8) vs exp(3) +/-*				1 test run
	sysrst_ctrl_combo_detect_with_pre_cond	57659488346412832175524036244059032713054801172949111386458627197378629977967	675	UVM_ERROR @ 13176513386 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(8) vs exp(3) +/-4 UVM_INFO @ 13176513386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---