Simulation Results

Simulation Results: sysrst_ctrl

08/05/2026 15:00:26 DVSim: v1.34.0 sha: afb7e07 json Branch: reseed_opt Tool: vcs [unknown]

Coverage statistics

Total
95.61 %

code
97.92 %

assert
97.89 %

func
91.03 %

line
99.33 %

branch
99.44 %

cond
97.88 %

toggle
100.00 %

FSM
92.95 %

Validation stages

V1		100.00%
V2		95.07%
V2S		100.00%
V3		100.00%

43/43 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	sysrst_ctrl_smoke	9.330s	2112.028us	10	10	100.00
input_output_inverted				10	10	100.00
	sysrst_ctrl_in_out_inverted	10.280s	2458.914us	10	10	100.00
combo_detect_ec_rst				5	5	100.00
	sysrst_ctrl_combo_detect_ec_rst	5.640s	2444.724us	5	5	100.00
combo_detect_ec_rst_with_pre_cond				5	5	100.00
	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	10.940s	2549.275us	5	5	100.00
csr_hw_reset				1	1	100.00
	sysrst_ctrl_csr_hw_reset	5.760s	6054.218us	1	1	100.00
csr_rw				5	5	100.00
	sysrst_ctrl_csr_rw	5.190s	2054.162us	5	5	100.00
csr_bit_bash				1	1	100.00
	sysrst_ctrl_csr_bit_bash	7.430s	4200.011us	1	1	100.00
csr_aliasing				1	1	100.00
	sysrst_ctrl_csr_aliasing	6.540s	3329.623us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	sysrst_ctrl_csr_mem_rw_with_rand_reset	5.610s	2115.407us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	sysrst_ctrl_csr_rw	5.190s	2054.162us	5	5	100.00
	sysrst_ctrl_csr_aliasing	6.540s	3329.623us	1	1	100.00

270/284 passed

95.07 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
combo_detect				10	10	100.00
	sysrst_ctrl_combo_detect	215.420s	86813.486us	10	10	100.00
combo_detect_with_pre_cond				92	100	92.00
	sysrst_ctrl_combo_detect_with_pre_cond	543.780s	210825.671us	92	100	92.00
auto_block_key_outputs				25	25	100.00
	sysrst_ctrl_auto_blk_key_output	554.230s	182784.115us	25	25	100.00
keyboard_input_triggered_interrupt				47	50	94.00
	sysrst_ctrl_edge_detect	601.640s	596784.312us	47	50	94.00
pin_output_keyboard_inversion_control				10	10	100.00
	sysrst_ctrl_pin_override_test	11.350s	2512.252us	10	10	100.00
pin_input_value_accessibility				10	10	100.00
	sysrst_ctrl_pin_access_test	8.900s	2151.585us	10	10	100.00
ec_power_on_reset				10	10	100.00
	sysrst_ctrl_ec_pwr_on_rst	1508.750s	817651.512us	10	10	100.00
flash_write_protect_output				10	10	100.00
	sysrst_ctrl_flash_wr_prot_out	10.960s	2610.324us	10	10	100.00
ultra_low_power_test				7	10	70.00
	sysrst_ctrl_ultra_low_pwr	6.640s	5899.790us	7	10	70.00
sysrst_ctrl_feature_disable				2	2	100.00
	sysrst_ctrl_feature_disable	64.130s	30246.940us	2	2	100.00
stress_all				10	10	100.00
	sysrst_ctrl_stress_all	382.550s	146366.698us	10	10	100.00
alert_test				10	10	100.00
	sysrst_ctrl_alert_test	7.320s	2011.465us	10	10	100.00
intr_test				10	10	100.00
	sysrst_ctrl_intr_test	9.540s	2009.693us	10	10	100.00
tl_d_oob_addr_access				5	5	100.00
	sysrst_ctrl_tl_errors	7.460s	2032.709us	5	5	100.00
tl_d_illegal_access				5	5	100.00
	sysrst_ctrl_tl_errors	7.460s	2032.709us	5	5	100.00
tl_d_outstanding_access				12	12	100.00
	sysrst_ctrl_csr_hw_reset	5.760s	6054.218us	1	1	100.00
	sysrst_ctrl_csr_rw	5.190s	2054.162us	5	5	100.00
	sysrst_ctrl_csr_aliasing	6.540s	3329.623us	1	1	100.00
	sysrst_ctrl_same_csr_outstanding	21.860s	7895.277us	5	5	100.00
tl_d_partial_access				12	12	100.00
	sysrst_ctrl_csr_hw_reset	5.760s	6054.218us	1	1	100.00
	sysrst_ctrl_csr_rw	5.190s	2054.162us	5	5	100.00
	sysrst_ctrl_csr_aliasing	6.540s	3329.623us	1	1	100.00
	sysrst_ctrl_same_csr_outstanding	21.860s	7895.277us	5	5	100.00

V2S

10/10 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				10	10	100.00
	sysrst_ctrl_sec_cm	67.840s	22051.369us	5	5	100.00
	sysrst_ctrl_tl_intg_err	126.810s	42412.441us	5	5	100.00
sec_cm_bus_integrity				5	5	100.00
	sysrst_ctrl_tl_intg_err	126.810s	42412.441us	5	5	100.00

10/10 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				10	10	100.00
	sysrst_ctrl_stress_all_with_rand_reset	67.090s	827744.525us	10	10	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error				5 test runs
	sysrst_ctrl_ultra_low_pwr	70107580581798277218021001414813524770850301741269365825750857953525053602664	659	UVM_ERROR @ 5249641424 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 5249641424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	2676621596901387849306258444171947584184197685829714926428006661372109702050	659	UVM_ERROR @ 4467850477 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 4467850477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	109173743676978976790133385647887446929694824047660421823559282154942620351807	665	UVM_ERROR @ 2695372853 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 2695372853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	86481491571420413710628949354839354830591871789733583045682268435749471586218	664	UVM_ERROR @ 2379225874 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 2379225874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	75453237298093000875151060452417050200645339759261798737951196558005869705664	662	UVM_ERROR @ 2531239786 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 2531239786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [] vs [*])				3 test runs
	sysrst_ctrl_combo_detect_with_pre_cond	82550093422128547119978444256254875558498103708875216148078957384566239131195	674	UVM_ERROR @ 28754442564 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 28754442564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_combo_detect_with_pre_cond	53412949926640846053853926940037642310485952459547319869143485989530066072022	666	UVM_INFO @ 23796276514 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2e UVM_INFO @ 23796297348 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x1c UVM_INFO @ 24895830419 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0 UVM_INFO @ 24910830419 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= b
	sysrst_ctrl_combo_detect_with_pre_cond	41354840340226987563842632806951451468569347046800386262398270961907378723517	679	UVM_ERROR @ 26050523481 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 26050523481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [] vs [*])				2 test runs
	sysrst_ctrl_combo_detect_with_pre_cond	3943610376817633640297595689393124870437930205976705841921144903167585629299	670	UVM_ERROR @ 16619349152 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 16619349152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_combo_detect_with_pre_cond	56333048163634018205181748018184764892249473768637077788240833981878740258678	684	UVM_INFO @ 51578949757 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2a UVM_INFO @ 51578991423 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x32 UVM_INFO @ 53408068380 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0 UVM_INFO @ 53408170489 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)				1 test run
	sysrst_ctrl_ultra_low_pwr	11059392244986061250924521849036658807606294529770360782711100434001722884238	658	UVM_ERROR @ 3320291485 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0]) UVM_INFO @ 3320291485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(9) vs exp(4) +/-*				1 test run
	sysrst_ctrl_combo_detect_with_pre_cond	24262674976098441428785805956816811206872573093546866637711748206848416116039	699	UVM_INFO @ 19249258690 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1 UVM_INFO @ 19269258690 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0 UVM_INFO @ 29421979175 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x21 UVM_INFO @ 29422685063 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x31
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(9) vs exp(4) +/-*				1 test run
	sysrst_ctrl_combo_detect_with_pre_cond	95902026559471994397019446785694194593832806039185736786527712374342587497624	668	UVM_ERROR @ 13855935226 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(9) vs exp(4) +/-4 UVM_INFO @ 13855935226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(10) vs exp(5) +/-*				1 test run
	sysrst_ctrl_combo_detect_with_pre_cond	106772533542182717928015278017569249250425838205272316743010079394544177343183	726	UVM_ERROR @ 70317985791 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(10) vs exp(5) +/-4 UVM_INFO @ 70317985791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---