Simulation Results: otbn

 
15/05/2026 15:00:24 DVSim: v1.34.0 sha: 9b0af25 json Branch: reseed_opt Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.95 %
  • code
  • 96.78 %
  • assert
  • 97.06 %
  • func
  • 100.00 %
  • block
  • 99.53 %
  • line
  • 99.64 %
  • branch
  • 94.10 %
  • toggle
  • 93.37 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.55%
V2S
97.87%
V3
50.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 39.000s 42.731us 1 1 100.00
single_binary 100 100 100.00
otbn_single 130.000s 375.479us 100 100 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 37.000s 64.136us 1 1 100.00
csr_rw 5 5 100.00
otbn_csr_rw 38.000s 37.412us 5 5 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 39.000s 96.728us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 37.000s 20.296us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
otbn_csr_mem_rw_with_rand_reset 40.000s 31.330us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otbn_csr_rw 38.000s 37.412us 5 5 100.00
otbn_csr_aliasing 37.000s 20.296us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 105.000s 11248.622us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 56.000s 525.725us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 50.000s 126.649us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 93.000s 171.747us 1 1 100.00
back_to_back 8 10 80.00
otbn_multi 156.000s 2795.966us 8 10 80.00
stress_all 9 10 90.00
otbn_stress_all 123.000s 1116.756us 9 10 90.00
lc_escalation 59 60 98.33
otbn_escalate 39.000s 29.629us 59 60 98.33
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 23.000s 39.455us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 105.000s 453.113us 10 10 100.00
alert_test 10 10 100.00
otbn_alert_test 37.000s 69.087us 10 10 100.00
intr_test 10 10 100.00
otbn_intr_test 37.000s 18.754us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otbn_tl_errors 27.000s 125.391us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otbn_tl_errors 27.000s 125.391us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otbn_csr_hw_reset 37.000s 64.136us 1 1 100.00
otbn_csr_rw 38.000s 37.412us 5 5 100.00
otbn_csr_aliasing 37.000s 20.296us 1 1 100.00
otbn_same_csr_outstanding 37.000s 33.252us 5 5 100.00
tl_d_partial_access 12 12 100.00
otbn_csr_hw_reset 37.000s 64.136us 1 1 100.00
otbn_csr_rw 38.000s 37.412us 5 5 100.00
otbn_csr_aliasing 37.000s 20.296us 1 1 100.00
otbn_same_csr_outstanding 37.000s 33.252us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 41.000s 32.869us 10 10 100.00
otbn_dmem_err 39.000s 56.827us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 107.000s 445.094us 5 5 100.00
otbn_controller_ispr_rdata_err 38.000s 76.198us 5 5 100.00
otbn_mac_bignum_acc_err 36.000s 185.250us 5 5 100.00
otbn_urnd_err 22.000s 16.221us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 36.000s 19.390us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 38.000s 23.375us 2 2 100.00
otbn_non_sec_partial_wipe 10 10 100.00
otbn_partial_wipe 38.000s 41.412us 10 10 100.00
tl_intg_err 30 30 100.00
otbn_sec_cm 303.000s 2613.750us 5 5 100.00
otbn_tl_intg_err 35.000s 192.897us 25 25 100.00
passthru_mem_tl_intg_err 4 5 80.00
otbn_passthru_mem_tl_intg_err 78.000s 345.419us 4 5 80.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 303.000s 2613.750us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 303.000s 2613.750us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 39.000s 42.731us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 39.000s 56.827us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 41.000s 32.869us 10 10 100.00
sec_cm_bus_integrity 25 25 100.00
otbn_tl_intg_err 35.000s 192.897us 25 25 100.00
sec_cm_controller_fsm_global_esc 59 60 98.33
otbn_escalate 39.000s 29.629us 59 60 98.33
sec_cm_controller_fsm_local_esc 40 40 100.00
otbn_imem_err 41.000s 32.869us 10 10 100.00
otbn_dmem_err 39.000s 56.827us 15 15 100.00
otbn_zero_state_err_urnd 23.000s 39.455us 5 5 100.00
otbn_illegal_mem_acc 36.000s 19.390us 5 5 100.00
otbn_sec_cm 303.000s 2613.750us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 303.000s 2613.750us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 130.000s 375.479us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 41.000s 32.869us 10 10 100.00
otbn_dmem_err 39.000s 56.827us 15 15 100.00
otbn_zero_state_err_urnd 23.000s 39.455us 5 5 100.00
otbn_illegal_mem_acc 36.000s 19.390us 5 5 100.00
otbn_sec_cm 303.000s 2613.750us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 303.000s 2613.750us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 59 60 98.33
otbn_escalate 39.000s 29.629us 59 60 98.33
sec_cm_start_stop_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 41.000s 32.869us 10 10 100.00
otbn_dmem_err 39.000s 56.827us 15 15 100.00
otbn_zero_state_err_urnd 23.000s 39.455us 5 5 100.00
otbn_illegal_mem_acc 36.000s 19.390us 5 5 100.00
otbn_sec_cm 303.000s 2613.750us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 303.000s 2613.750us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 130.000s 375.479us 100 100 100.00
sec_cm_ctrl_redun 11 12 91.67
otbn_ctrl_redun 40.000s 26.170us 11 12 91.67
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 41.000s 30.952us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 130.000s 639.872us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 130.000s 639.872us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 39.000s 51.070us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 303.000s 2613.750us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 303.000s 2613.750us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 9 10 90.00
otbn_rf_bignum_intg_err 36.000s 908.751us 9 10 90.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 303.000s 2613.750us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 303.000s 2613.750us 5 5 100.00
sec_cm_loop_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 39.000s 73.656us 4 5 80.00
sec_cm_call_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 39.000s 73.656us 4 5 80.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 37.000s 106.221us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 130.000s 375.479us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 130.000s 375.479us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 130.000s 375.479us 100 100 100.00
sec_cm_write_mem_integrity 8 10 80.00
otbn_multi 156.000s 2795.966us 8 10 80.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 130.000s 375.479us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 130.000s 375.479us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 34.000s 71.307us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 130.000s 375.479us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 303.000s 2613.750us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
otbn_stress_all_with_rand_reset 382.000s 3897.758us 5 10 50.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 36.000s 22.307us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) 2 test runs
otbn_stress_all_with_rand_reset 60037831987168112997960773100096161284081939460169845248935048178124918126995 297
UVM_INFO @ 2601401016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 99737781640643878971011115238060964040630541518631561917045358230397948996773 167
UVM_INFO @ 39999323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 2 test runs
otbn_multi 15007617263723757525719410216213974378809729933238366310626693380340151410523 151
UVM_INFO @ 133871241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_multi 58948218745721556878764282627806022638817616673882114451913587908623274845093 151
UVM_INFO @ 180592943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 2 test runs
otbn_rf_bignum_intg_err 95601258392882952465864643008670879509122803193601301678586612403545784179640 114
UVM_INFO @ 308695614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 61453344426455722699628830356856079347416323643014892009549859173744389683933 165
UVM_INFO @ 39117495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 2 test runs
otbn_stress_all 54507457739257647581859553110694787309555097908920051242160341768411214243889 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
otbn_escalate 50671475478322482025509854798427162769928754664491378786934689853970009400826 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
xmsim: *E,ASRTST (/nightly/current_run/scratch/reseed_opt/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 1 test run
otbn_stack_addr_integ_chk 102193936541470592664585292024613374236102074598471678224842236977668185362769 123
xmsim: *E,ASRTST (/nightly/current_run/scratch/reseed_opt/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 73655845 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 73655845 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 73655845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. 1 test run
otbn_passthru_mem_tl_intg_err 110796019206238180419810610600735821333564774054886390269297020513263959813302 86
UVM_INFO @ 2225825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 98040312744644610537468755506342033882193783369245650780221735405684359323816 355
UVM_INFO @ 3897758482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 73703981184056594730889318306173080230861249365616140577605344632451685332094 305
UVM_INFO @ 827434992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/reseed_opt/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn_controller.sv,703): Assertion NoStallOnBranch has failed 1 test run
otbn_ctrl_redun 86143493797706916425942453818600807179402602134854088745599165258554049493596 116
UVM_ERROR @ 167106879 ps: (otbn_controller.sv:703) [ASSERT FAILED] NoStallOnBranch
UVM_INFO @ 167106879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---