| V1 |
|
100.00% |
| V2 |
|
77.04% |
| V2S |
|
100.00% |
| V3 |
|
6.00% |
| unmapped |
|
68.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 50 | 50 | 100.00 | |||
| pattgen_smoke | 4.000s | 111.789us | 50 | 50 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| pattgen_csr_hw_reset | 1.000s | 27.326us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| pattgen_csr_rw | 2.000s | 25.109us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| pattgen_csr_bit_bash | 2.000s | 102.635us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| pattgen_csr_aliasing | 2.000s | 17.610us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| pattgen_csr_mem_rw_with_rand_reset | 2.000s | 27.172us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| pattgen_csr_rw | 2.000s | 25.109us | 5 | 5 | 100.00 | |
| pattgen_csr_aliasing | 2.000s | 17.610us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| perf | 25 | 50 | 50.00 | |||
| pattgen_perf | 3602.080s | 0.000us | 25 | 50 | 50.00 | |
| cnt_rollover | 50 | 50 | 100.00 | |||
| cnt_rollover | 53.000s | 2676.237us | 50 | 50 | 100.00 | |
| error | 50 | 50 | 100.00 | |||
| pattgen_error | 2.000s | 17.280us | 50 | 50 | 100.00 | |
| stress_all | 16 | 50 | 32.00 | |||
| pattgen_stress_all | 10802.188s | 0.000us | 16 | 50 | 32.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| pattgen_alert_test | 2.000s | 132.404us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| pattgen_intr_test | 2.000s | 37.695us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| pattgen_tl_errors | 3.000s | 67.035us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| pattgen_tl_errors | 3.000s | 67.035us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| pattgen_csr_hw_reset | 1.000s | 27.326us | 1 | 1 | 100.00 | |
| pattgen_csr_rw | 2.000s | 25.109us | 5 | 5 | 100.00 | |
| pattgen_csr_aliasing | 2.000s | 17.610us | 1 | 1 | 100.00 | |
| pattgen_same_csr_outstanding | 2.000s | 14.118us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| pattgen_csr_hw_reset | 1.000s | 27.326us | 1 | 1 | 100.00 | |
| pattgen_csr_rw | 2.000s | 25.109us | 5 | 5 | 100.00 | |
| pattgen_csr_aliasing | 2.000s | 17.610us | 1 | 1 | 100.00 | |
| pattgen_same_csr_outstanding | 2.000s | 14.118us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| pattgen_tl_intg_err | 2.000s | 66.943us | 25 | 25 | 100.00 | |
| pattgen_sec_cm | 2.000s | 74.882us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| pattgen_tl_intg_err | 2.000s | 66.943us | 25 | 25 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 3 | 50 | 6.00 | |||
| pattgen_stress_all_with_rand_reset | 118.000s | 17304.641us | 3 | 50 | 6.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 34 | 50 | 68.00 | |||
| pattgen_inactive_level | 219.000s | 10004.789us | 34 | 50 | 68.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 47 test runs | |||
| pattgen_stress_all_with_rand_reset | 63664425844087122589158745132939872305192886662026993875930476105319630932598 | 190 |
UVM_ERROR @ 5832246787 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 5832246787 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 5832406787 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 45298523475039433245733595696573499112036375292555662935804936585816511573466 | 219 |
UVM_ERROR @ 4073550088 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 4073550088 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/5
UVM_INFO @ 4073670088 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 112941098879191363902685801605348338197492236751304684450510026336939392516923 | 175 |
UVM_ERROR @ 4884269900 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 4884269900 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 4884353234 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 42574758852887082795343900011520206242905151651687256864859217184747918684435 | 243 |
UVM_ERROR @ 1432914910 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1432914910 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 1432945522 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 93000167162377439687301519720692877997830143128948417348496287688612598713970 | 153 |
UVM_ERROR @ 2963382293 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2963382293 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 2963502293 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 26313413082085389253503977516853681255851919092592352534998859883331017296593 | 229 |
UVM_ERROR @ 2451560001 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2451560001 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/10
UVM_INFO @ 2451755652 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 27463143123613021159546180482509948709730169978448602080417818067773933051248 | 213 |
UVM_ERROR @ 407764905 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 407764905 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 407858658 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 27069608932020877636806998486283269303307521041245554975277149423282394157957 | 113 |
UVM_ERROR @ 218889572 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 218889572 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 218929572 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 48114396132584867902877169974087235363108326339394690354082606981457721488861 | 122 |
UVM_ERROR @ 705377050 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 705377050 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 705427050 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 99190342536990761808039501394486687345443678064355603726234226704522429550274 | 168 |
UVM_ERROR @ 8305649650 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 8305649650 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 8305803496 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 108210555840187037011377333250914942848653462295778122852999415953039944010392 | 232 |
UVM_ERROR @ 2313850259 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2313850259 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 2313970259 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 14105207356221648441214564064193696497466127459143423520005872214442071853291 | 131 |
UVM_ERROR @ 1023225263 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1023225263 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 1023275263 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 68604181529767675874397874947460988522177574593548712519685611625580980297745 | 146 |
UVM_ERROR @ 1246401784 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1246401784 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 1246681784 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 70318056321160151364948819086992591093501101879718552434824680957953541884813 | 115 |
UVM_ERROR @ 310872496 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 310872496 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 310941460 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 32705347829179141435238787459417960760597069812166192754180647374653682787678 | 113 |
UVM_ERROR @ 207312868 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 207312868 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 207389792 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 106728593822904317049527019664425833600665879369766240856231649201369521681741 | 152 |
UVM_ERROR @ 932861880 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 932861880 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 932933308 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 114447073043091560947190772822499196326135013044142336178196458010316454848329 | 255 |
UVM_ERROR @ 4148790054 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 4148790054 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 4148890054 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 45881070075579599673925980168730489110241009572077356501730386211241573012030 | 119 |
UVM_ERROR @ 1652369587 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1652369587 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 1652661256 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 51919673234324808812866010790930141971861524346803880766039242002844031128121 | 131 |
UVM_ERROR @ 3106117582 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3106117582 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 3106357582 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 48692588253719394383880221851734812387171545546125648693781306136349148655571 | 176 |
UVM_ERROR @ 3803866214 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3803866214 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 3803991215 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 41405824313259552628313335675949966974819793579710884916688337631491788099084 | 124 |
UVM_ERROR @ 405208213 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 405208213 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 405281132 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 35846918972682023378611951534238176104322652295575090344901886674712979019135 | 151 |
UVM_ERROR @ 858030553 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 858030553 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 858120553 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 91397580258664683380349386718822209148697849334723754100088430556152374366790 | 293 |
UVM_ERROR @ 7417582216 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 7417582216 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 7/10
UVM_INFO @ 7417748884 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 11857400305120162570840416919308141597418632791101882454056058873821086672319 | 156 |
UVM_ERROR @ 6594450977 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 6594450977 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 6594867647 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 44017837583673914426415393450246589717777583384539661425158532214085726279171 | 119 |
UVM_ERROR @ 1811969481 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1811969481 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1812177811 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 105483291426416147225105380076987772453368598121067645583506975205671932274502 | 143 |
UVM_ERROR @ 230576800 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 230576800 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 230668636 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 55477358546031040330520063032996097933529038063730849201949905347826453533326 | 139 |
UVM_ERROR @ 2037635346 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2037635346 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 2037775346 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 74716215403941102511187546198225632942263833580495166179400398691459550726042 | 226 |
UVM_ERROR @ 1533339387 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1533339387 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 1533429387 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 103110391204464350010839467602903230326987133370860891021826094218085790369416 | 381 |
UVM_ERROR @ 7731220732 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 7731220732 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 7/10
UVM_INFO @ 7731363588 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 31466089709632296427538259020207940367429558696329490396906060802278516633479 | 113 |
UVM_ERROR @ 798194261 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 798194261 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 798348107 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 67693336483640819170841608536009881542253352625811484374321154555447764954428 | 161 |
UVM_ERROR @ 1020352921 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1020352921 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 1020384172 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 54874611665670097900699787307747794289953510807560170236316415178891072255502 | 178 |
UVM_ERROR @ 6404466408 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 6404466408 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 6404819352 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 87928515076600477575903239116707887665648256436084370516411440370028802333429 | 113 |
UVM_ERROR @ 1770986366 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1770986366 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1771804547 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 35660589465675244294284018482082367751417876969491123597087094437712927142071 | 139 |
UVM_ERROR @ 878095786 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 878095786 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 878146291 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 42254919935839822514242128971997563184133726483804077949449980947881659705971 | 225 |
UVM_ERROR @ 10322581440 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 10322581440 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 10322893940 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 90159363536972361533058025409716290997799813214177623006448220589132483216531 | 222 |
UVM_ERROR @ 15777644828 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 15777644828 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 15778089272 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 43298937932386399884958055257689322224216266043993045915636839870753114407126 | 115 |
UVM_ERROR @ 1100314458 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1100314458 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 1100606127 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 110128453249833101556310789523406300604285883547090682771654219024118967081501 | 127 |
UVM_ERROR @ 652381245 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 652381245 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 652504536 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 57342474429637156680739871522191281073972355470744412278944549601485189291038 | 123 |
UVM_ERROR @ 1665704587 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1665704587 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1665827035 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 103953567633769209617323114378121613186761613209506347702071432093721319460861 | 156 |
UVM_ERROR @ 400342798 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 400342798 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 400427902 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 61931082521537079580218998471250330836445082079184176083145056752770653777848 | 220 |
UVM_ERROR @ 2319270786 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2319270786 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/10
UVM_INFO @ 2319354118 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 20699915685056312796640624646530654096225231240070030188879787578623986671778 | 148 |
UVM_ERROR @ 764170565 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 764170565 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 764250565 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 88986541862856392604319575409015693836480117622845408526911653690040881088048 | 212 |
UVM_ERROR @ 4510588339 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 4510588339 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 4510838341 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 93509903989679560883750040189282545038897711582965023117677179807880207955948 | 116 |
UVM_ERROR @ 603331050 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 603331050 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 603382595 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 112516783217651301199465672483672081012466367771576064769270286544758966874679 | 148 |
UVM_ERROR @ 4860327719 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 4860327719 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 4860549941 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 9885668029430294706012857903487418311272585421966683820620361681017978376148 | 193 |
UVM_ERROR @ 3830299489 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3830299489 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 3830503569 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 85143728641321754431409311907221001755255518266935443975870703884774292115685 | 193 |
UVM_ERROR @ 766085336 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 766085336 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/5
UVM_INFO @ 766269008 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: | 25 test runs | |||
| pattgen_stress_all | 64622999860352081434829406955428869140425901831667138575956927361469811456624 | 138 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11210
|
|
| pattgen_stress_all | 88492660791072610510624446766447982057532094047411416042099480032040631372016 | 125 |
--------------------------------------
Name Type Size Value
--------------------------------------
exp_item pattgen_item - @11320
|
|
| pattgen_stress_all | 76486680787706223185072363314992328966649300559299567018790144204388078877473 | 125 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11297
|
|
| pattgen_stress_all | 8242407274412457680841796590693452101759885742499895948229689880636665093652 | 150 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11660
|
|
| pattgen_stress_all | 95058014978389046187537357831371740760174017165918106443545740556104970683486 | 125 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11318
|
|
| pattgen_stress_all | 18776961696513643545494535842482139053529254854040058716522357358514496126314 | 144 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11322
|
|
| pattgen_stress_all | 76761698584430003412693025664626196831482592350629446934688399754397714565672 | 150 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11361
|
|
| pattgen_stress_all | 108565683873923541769006625013799049409557370381491196929617116819353191847080 | 152 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11365
|
|
| pattgen_stress_all | 99009050127150702140681459489803695297755649986147314544926876483513544350758 | 130 |
--------------------------------------
Name Type Size Value
--------------------------------------
exp_item pattgen_item - @11338
|
|
| pattgen_stress_all | 115052942165181897758777849353959887671324277621119386896191869254782147594125 | 146 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11228
|
|
| pattgen_stress_all | 85619209953390358108326955533916638974184448642192997382084585226309750692236 | 125 |
--------------------------------------
Name Type Size Value
--------------------------------------
exp_item pattgen_item - @11346
|
|
| pattgen_stress_all | 68611455523502374633243627638959952040805096277391186272873188224663481360019 | 137 |
--------------------------------------
Name Type Size Value
--------------------------------------
exp_item pattgen_item - @13801
|
|
| pattgen_stress_all | 110861797356895819884458182443465336185810746961618266397437273800271825681937 | 137 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11344
|
|
| pattgen_stress_all | 9613611996052735957464967571273993085187140793063840193329859635774164238206 | 132 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11393
|
|
| pattgen_stress_all | 107360642219078771344163686641068474264929516310413983450613388906764205764358 | 156 |
--------------------------------------
Name Type Size Value
--------------------------------------
exp_item pattgen_item - @11330
|
|
| pattgen_stress_all | 89528906654742628074799006969497283611450204571728166436531377273039498791493 | 125 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11318
|
|
| pattgen_stress_all | 20701385587416416284447550270380109606389478743472522308660388748073122930747 | 135 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11301
|
|
| pattgen_stress_all | 113642203109368422857073630803181139233057390164735714272189082425212641231605 | 157 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11250
|
|
| pattgen_stress_all | 97326733885779274157038518982449507625204489656076189468334945233300364597199 | 138 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11374
|
|
| pattgen_stress_all | 31508883322020846969177351739863655414932043278599998518055037841320415966494 | 158 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11371
|
|
| pattgen_stress_all | 10973904522708312208461274605715151183794613007461967973124633930924291796935 | 139 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11304
|
|
| pattgen_stress_all | 69186789389166917803584332787874757523749446250084873128952965896115536594419 | 142 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11256
|
|
| pattgen_stress_all | 28272316119802842003585290634645347625551762997594305404529078254108298153124 | 145 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11313
|
|
| pattgen_stress_all | 27714646371069491095664142994871807031066518309206417957297527182351732008490 | 125 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11330
|
|
| pattgen_stress_all | 38577756178503217935766325175100787234047740218016942808420929605126829314716 | 136 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11336
|
|
| Job timed out after * minutes | 21 test runs | |||
| pattgen_stress_all | 30799377806995657245075993569045488899639700550915192369006154463096018841805 | None | ||
| pattgen_stress_all | 112380411775351786385408895266396040186907934539994868600629691628643246215401 | None | ||
| pattgen_perf | 20345033683141215507644970552525720479335421011665824912283238633492285978026 | None | ||
| pattgen_perf | 16908935432764007173088864113128944075457416383604400963251805055066172817024 | None | ||
| pattgen_perf | 107221121793471302905634789167353868277332712114546963129815573809406301239737 | None | ||
| pattgen_perf | 104948752952173026915770125615081539982495752293670626783852260384534254276998 | None | ||
| pattgen_perf | 63836519880160658079231473705346619336449112940674151700720498687402381913113 | None | ||
| pattgen_perf | 50625106788795327952324236096849161859460563162312631441073049789573588298312 | None | ||
| pattgen_perf | 89010586500136493376738762724235358193527614227284175539229758061545747459286 | None | ||
| pattgen_stress_all | 110011712854611703037301833309817535890526132727085042186931618613410105482114 | None | ||
| pattgen_stress_all | 109647269942191541149468828968997782723661664134469005230590822936337162612511 | None | ||
| pattgen_stress_all | 82171851693071013888053837199813511847457803579583041954639142665906716337269 | None | ||
| pattgen_perf | 14030813974727348255803368830357477353461227851604930192588124707683270904920 | None | ||
| pattgen_perf | 80646158577297814649247746025235157706645777267526636679285274514933983589951 | None | ||
| pattgen_perf | 98169306197364599298656627548312604911677975867071661843477775235613688109578 | None | ||
| pattgen_stress_all | 82629258564493771745574593661073403196347250532142087905998259391980535349060 | None | ||
| pattgen_stress_all | 10170378567455627654810144718274890779640529749692156207968082748936970759755 | None | ||
| pattgen_perf | 76670192381768482078997653008995790863265334392790848701132630379363202636131 | None | ||
| pattgen_stress_all | 66326239134299074034355524297103042026308985610731791714392503715039223904608 | None | ||
| pattgen_perf | 20889032130331542231380217434936387560787737560803375262452374642154649200564 | None | ||
| pattgen_stress_all | 108965211474823382475624449664962997648324837544357782916392421929940172583947 | None | ||
| UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | 13 test runs | |||
| pattgen_perf | 88465880918281392326831310877427614059040324742116005186964689793041991869698 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 15345269413096276406240140164984919985293972959790348930184534014259014886798 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 49940049796213515374208423473316246320138657869017462732828419635572938747421 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 113357637880891671485559814940777015985914030892146298755777616557679282772699 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 88345296231924555244287940424304277168742206699361952651781912022675303829261 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 36458092848558846925634860140074301072908780055650749298192383232443127302629 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 61140894552662430511005682102147976294533996223041113746557614572034721411010 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 9767228568951402026688117906381976179479570061013640683836580867184247723318 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 29563864623536126596346222356822315703406897609238159445714315093235292740275 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 30080057314744963213406431786306477343036075341579331836568532270684650945047 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 113680274923018420935647024128888079711476378392227211591991531981241691270646 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 95876471704210191364566442422137872766021049403742426768836857345300187253751 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 90750938462007480229864416091998598068739596142662881357397261883102652785579 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=24) | 2 test runs | |||
| pattgen_inactive_level | 97374863045150140436605002402539334835969377174939219161278382657533457663466 | 99 |
UVM_INFO @ 10057622841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 74667067796497020952094691463225466381101659341560079717357401222561336094992 | 99 |
UVM_INFO @ 10035156079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) | 2 test runs | |||
| pattgen_inactive_level | 107856460396545831776271568164754428592671863189809626610634359388482014837177 | 99 |
UVM_INFO @ 10006713316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 10457015939023883772339991098950286739828803430071820853843347022484226287655 | 99 |
UVM_INFO @ 10025046662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22) | 2 test runs | |||
| pattgen_inactive_level | 55494784206449830617567917099272241328131828532725560293863292066250746661180 | 99 |
UVM_INFO @ 10034514057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 61931922210672533817324838139256288457944893830621379544749728343685356218472 | 99 |
UVM_INFO @ 10097296601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) | 2 test runs | |||
| pattgen_inactive_level | 64820610012703628763858910998594025296407387480208435856002849293121321455423 | 99 |
UVM_INFO @ 10078094909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 32519799926210258584719339182652120080300837660361240252425633665270499424835 | 99 |
UVM_INFO @ 10004789180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) | 2 test runs | |||
| pattgen_inactive_level | 66456598290830782919624721258165026907970164909529057083263703405803398077816 | 99 |
UVM_INFO @ 10015414079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 85414713190295624714502466229614946510090080209270957885558092694102321990081 | 99 |
UVM_INFO @ 10045214568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) | 2 test runs | |||
| pattgen_inactive_level | 111452288551774690251568180323459755489732089927922542861086309995788706190030 | 99 |
UVM_INFO @ 10143888247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 70667603732983592489902547711294943632142422530555728874720601732006473112210 | 99 |
UVM_INFO @ 10147974725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) | 2 test runs | |||
| pattgen_inactive_level | 31954569629629427489482085497221595435526018840448321689144690543809877511982 | 99 |
UVM_INFO @ 10022094384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 52661400772015275574163313822390921195030234839772571168289123765024816995729 | 99 |
UVM_INFO @ 10020144856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) | 1 test run | |||
| pattgen_inactive_level | 2554214035152763742507431239551649579682419375296763183800622135120422941107 | 99 |
UVM_INFO @ 10042857442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) | 1 test run | |||
| pattgen_inactive_level | 78324656139627727031444962023035213032099711483700208969725204632996495508096 | 99 |
UVM_INFO @ 10022184582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|