| V1 |
|
97.66% |
| V2 |
|
85.83% |
| V2S |
|
100.00% |
| V3 |
|
81.76% |
| unmapped |
|
67.74% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_example_tests | 12 | 12 | 100.00 | |||
| chip_sw_example_flash | 225.380s | 2873.453us | 3 | 3 | 100.00 | |
| chip_sw_example_rom | 110.440s | 2139.104us | 3 | 3 | 100.00 | |
| chip_sw_example_manufacturer | 235.330s | 3242.586us | 3 | 3 | 100.00 | |
| chip_sw_example_concurrency | 231.610s | 3041.457us | 3 | 3 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| chip_csr_hw_reset | 436.790s | 6506.719us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| chip_csr_rw | 645.770s | 6323.238us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| chip_csr_bit_bash | 414.990s | 4995.994us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| chip_csr_aliasing | 6401.140s | 37984.840us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 2 | 5 | 40.00 | |||
| chip_csr_mem_rw_with_rand_reset | 779.230s | 9557.541us | 2 | 5 | 40.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| chip_csr_aliasing | 6401.140s | 37984.840us | 1 | 1 | 100.00 | |
| chip_csr_rw | 645.770s | 6323.238us | 5 | 5 | 100.00 | |
| xbar_smoke | 50 | 50 | 100.00 | |||
| xbar_smoke | 11.790s | 224.789us | 50 | 50 | 100.00 | |
| chip_sw_gpio_out | 3 | 3 | 100.00 | |||
| chip_sw_gpio | 415.210s | 4473.916us | 3 | 3 | 100.00 | |
| chip_sw_gpio_in | 3 | 3 | 100.00 | |||
| chip_sw_gpio | 415.210s | 4473.916us | 3 | 3 | 100.00 | |
| chip_sw_gpio_irq | 3 | 3 | 100.00 | |||
| chip_sw_gpio | 415.210s | 4473.916us | 3 | 3 | 100.00 | |
| chip_sw_uart_tx_rx | 5 | 5 | 100.00 | |||
| chip_sw_uart_tx_rx | 525.490s | 5033.631us | 5 | 5 | 100.00 | |
| chip_sw_uart_rx_overflow | 20 | 20 | 100.00 | |||
| chip_sw_uart_tx_rx | 525.490s | 5033.631us | 5 | 5 | 100.00 | |
| chip_sw_uart_tx_rx_idx1 | 485.430s | 4630.361us | 5 | 5 | 100.00 | |
| chip_sw_uart_tx_rx_idx2 | 501.880s | 4535.433us | 5 | 5 | 100.00 | |
| chip_sw_uart_tx_rx_idx3 | 500.450s | 4455.739us | 5 | 5 | 100.00 | |
| chip_sw_uart_baud_rate | 20 | 20 | 100.00 | |||
| chip_sw_uart_rand_baudrate | 2619.900s | 12971.774us | 20 | 20 | 100.00 | |
| chip_sw_uart_tx_rx_alt_clk_freq | 10 | 10 | 100.00 | |||
| chip_sw_uart_tx_rx_alt_clk_freq | 2289.610s | 13485.608us | 5 | 5 | 100.00 | |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 1328.170s | 13227.531us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_pin_mux | 10 | 10 | 100.00 | |||
| chip_padctrl_attributes | 324.570s | 5654.047us | 10 | 10 | 100.00 | |
| chip_padctrl_attributes | 10 | 10 | 100.00 | |||
| chip_padctrl_attributes | 324.570s | 5654.047us | 10 | 10 | 100.00 | |
| chip_sw_sleep_pin_mio_dio_val | 2 | 3 | 66.67 | |||
| chip_sw_sleep_pin_mio_dio_val | 248.100s | 3049.941us | 2 | 3 | 66.67 | |
| chip_sw_sleep_pin_wake | 2 | 3 | 66.67 | |||
| chip_sw_sleep_pin_wake | 337.330s | 6392.669us | 2 | 3 | 66.67 | |
| chip_sw_sleep_pin_retention | 3 | 3 | 100.00 | |||
| chip_sw_sleep_pin_retention | 286.660s | 4130.098us | 3 | 3 | 100.00 | |
| chip_sw_tap_strap_sampling | 20 | 20 | 100.00 | |||
| chip_tap_straps_dev | 1189.180s | 13885.673us | 5 | 5 | 100.00 | |
| chip_tap_straps_testunlock0 | 709.110s | 9470.777us | 5 | 5 | 100.00 | |
| chip_tap_straps_rma | 554.330s | 6903.002us | 5 | 5 | 100.00 | |
| chip_tap_straps_prod | 1510.170s | 17767.199us | 5 | 5 | 100.00 | |
| chip_sw_pattgen_ios | 3 | 3 | 100.00 | |||
| chip_sw_pattgen_ios | 265.550s | 3725.492us | 3 | 3 | 100.00 | |
| chip_sw_sleep_pwm_pulses | 3 | 3 | 100.00 | |||
| chip_sw_sleep_pwm_pulses | 1029.730s | 9270.343us | 3 | 3 | 100.00 | |
| chip_sw_data_integrity | 6 | 6 | 100.00 | |||
| chip_sw_data_integrity_escalation | 684.370s | 6459.827us | 6 | 6 | 100.00 | |
| chip_sw_instruction_integrity | 6 | 6 | 100.00 | |||
| chip_sw_data_integrity_escalation | 684.370s | 6459.827us | 6 | 6 | 100.00 | |
| chip_sw_ast_clk_outputs | 3 | 3 | 100.00 | |||
| chip_sw_ast_clk_outputs | 878.860s | 8234.277us | 3 | 3 | 100.00 | |
| chip_sw_ast_clk_rst_inputs | 0 | 3 | 0.00 | |||
| chip_sw_ast_clk_rst_inputs | 1738.970s | 13507.709us | 0 | 3 | 0.00 | |
| chip_sw_ast_sys_clk_jitter | 30 | 30 | 100.00 | |||
| chip_sw_flash_ctrl_ops_jitter_en | 511.300s | 4064.858us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_access_jitter_en | 806.670s | 6134.225us | 3 | 3 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 5004.400s | 19166.932us | 3 | 3 | 100.00 | |
| chip_sw_aes_enc_jitter_en | 232.320s | 2471.461us | 3 | 3 | 100.00 | |
| chip_sw_edn_entropy_reqs_jitter | 998.490s | 7711.046us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_jitter_en | 251.720s | 3562.638us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation_jitter_en | 2284.930s | 12101.103us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 270.240s | 3160.523us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 567.030s | 5850.868us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_jitter | 177.380s | 2345.385us | 3 | 3 | 100.00 | |
| chip_sw_ast_usb_clk_calib | 1 | 1 | 100.00 | |||
| chip_sw_usb_ast_clk_calib | 290.580s | 3768.172us | 1 | 1 | 100.00 | |
| chip_sw_sensor_ctrl_ast_alerts | 8 | 8 | 100.00 | |||
| chip_sw_sensor_ctrl_alert | 886.710s | 9514.008us | 5 | 5 | 100.00 | |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 359.310s | 6030.646us | 3 | 3 | 100.00 | |
| chip_sw_sensor_ctrl_ast_status | 3 | 3 | 100.00 | |||
| chip_sw_sensor_ctrl_status | 248.130s | 2994.656us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 359.310s | 6030.646us | 3 | 3 | 100.00 | |
| chip_sw_smoketest | 51 | 51 | 100.00 | |||
| chip_sw_flash_scrambling_smoketest | 231.960s | 3163.532us | 3 | 3 | 100.00 | |
| chip_sw_aes_smoketest | 249.470s | 2996.778us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_smoketest | 287.070s | 3377.732us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_smoketest | 205.790s | 3454.555us | 3 | 3 | 100.00 | |
| chip_sw_csrng_smoketest | 212.490s | 2773.660us | 3 | 3 | 100.00 | |
| chip_sw_entropy_src_smoketest | 1353.600s | 8190.399us | 3 | 3 | 100.00 | |
| chip_sw_gpio_smoketest | 241.420s | 3374.895us | 3 | 3 | 100.00 | |
| chip_sw_hmac_smoketest | 290.510s | 3754.363us | 3 | 3 | 100.00 | |
| chip_sw_kmac_smoketest | 262.450s | 3140.767us | 3 | 3 | 100.00 | |
| chip_sw_otbn_smoketest | 1959.350s | 10093.799us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_smoketest | 329.260s | 6259.162us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_usbdev_smoketest | 404.800s | 6364.446us | 3 | 3 | 100.00 | |
| chip_sw_rv_plic_smoketest | 230.600s | 3125.136us | 3 | 3 | 100.00 | |
| chip_sw_rv_timer_smoketest | 224.840s | 3000.110us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_smoketest | 226.260s | 2717.643us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_smoketest | 218.390s | 2961.333us | 3 | 3 | 100.00 | |
| chip_sw_uart_smoketest | 227.710s | 2911.964us | 3 | 3 | 100.00 | |
| chip_sw_otp_smoketest | 3 | 3 | 100.00 | |||
| chip_sw_otp_ctrl_smoketest | 226.440s | 3204.333us | 3 | 3 | 100.00 | |
| chip_sw_rom_functests | 0 | 3 | 0.00 | |||
| rom_keymgr_functest | 457.210s | 5140.982us | 0 | 3 | 0.00 | |
| chip_sw_boot | 3 | 3 | 100.00 | |||
| chip_sw_uart_tx_rx_bootstrap | 13282.510s | 62815.127us | 3 | 3 | 100.00 | |
| chip_sw_secure_boot | 3 | 3 | 100.00 | |||
| rom_e2e_smoke | 3864.500s | 15016.578us | 3 | 3 | 100.00 | |
| chip_sw_rom_raw_unlock | 0 | 3 | 0.00 | |||
| rom_raw_unlock | 89.622s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_power_idle_load | 0 | 3 | 0.00 | |||
| chip_sw_power_idle_load | 272.480s | 3616.411us | 0 | 3 | 0.00 | |
| chip_sw_power_sleep_load | 0 | 3 | 0.00 | |||
| chip_sw_power_sleep_load | 250.840s | 3576.870us | 0 | 3 | 0.00 | |
| chip_sw_exit_test_unlocked_bootstrap | 3 | 3 | 100.00 | |||
| chip_sw_exit_test_unlocked_bootstrap | 11762.680s | 55778.263us | 3 | 3 | 100.00 | |
| chip_sw_inject_scramble_seed | 3 | 3 | 100.00 | |||
| chip_sw_inject_scramble_seed | 12392.220s | 58576.137us | 3 | 3 | 100.00 | |
| tl_d_oob_addr_access | 2 | 30 | 6.67 | |||
| chip_tl_errors | 491.730s | 4778.952us | 2 | 30 | 6.67 | |
| tl_d_illegal_access | 2 | 30 | 6.67 | |||
| chip_tl_errors | 491.730s | 4778.952us | 2 | 30 | 6.67 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| chip_csr_aliasing | 6401.140s | 37984.840us | 1 | 1 | 100.00 | |
| chip_same_csr_outstanding | 3671.830s | 28503.231us | 5 | 5 | 100.00 | |
| chip_csr_hw_reset | 436.790s | 6506.719us | 1 | 1 | 100.00 | |
| chip_csr_rw | 645.770s | 6323.238us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| chip_csr_aliasing | 6401.140s | 37984.840us | 1 | 1 | 100.00 | |
| chip_same_csr_outstanding | 3671.830s | 28503.231us | 5 | 5 | 100.00 | |
| chip_csr_hw_reset | 436.790s | 6506.719us | 1 | 1 | 100.00 | |
| chip_csr_rw | 645.770s | 6323.238us | 5 | 5 | 100.00 | |
| xbar_base_random_sequence | 50 | 50 | 100.00 | |||
| xbar_random | 79.870s | 2067.948us | 50 | 50 | 100.00 | |
| xbar_random_delay | 300 | 300 | 100.00 | |||
| xbar_smoke_zero_delays | 8.170s | 54.635us | 50 | 50 | 100.00 | |
| xbar_smoke_large_delays | 108.750s | 10346.730us | 50 | 50 | 100.00 | |
| xbar_smoke_slow_rsp | 104.120s | 7185.840us | 50 | 50 | 100.00 | |
| xbar_random_zero_delays | 54.140s | 601.135us | 50 | 50 | 100.00 | |
| xbar_random_large_delays | 432.840s | 54820.381us | 50 | 50 | 100.00 | |
| xbar_random_slow_rsp | 435.000s | 34407.589us | 50 | 50 | 100.00 | |
| xbar_unmapped_address | 100 | 100 | 100.00 | |||
| xbar_unmapped_addr | 54.500s | 1466.678us | 50 | 50 | 100.00 | |
| xbar_error_and_unmapped_addr | 50.710s | 1334.340us | 50 | 50 | 100.00 | |
| xbar_error_cases | 100 | 100 | 100.00 | |||
| xbar_error_random | 76.940s | 2412.711us | 50 | 50 | 100.00 | |
| xbar_error_and_unmapped_addr | 50.710s | 1334.340us | 50 | 50 | 100.00 | |
| xbar_all_access_same_device | 100 | 100 | 100.00 | |||
| xbar_access_same_device | 131.220s | 3101.471us | 50 | 50 | 100.00 | |
| xbar_access_same_device_slow_rsp | 1151.260s | 88770.150us | 50 | 50 | 100.00 | |
| xbar_all_hosts_use_same_source_id | 50 | 50 | 100.00 | |||
| xbar_same_source | 74.070s | 2267.824us | 50 | 50 | 100.00 | |
| xbar_stress_all | 100 | 100 | 100.00 | |||
| xbar_stress_all | 573.000s | 19517.884us | 50 | 50 | 100.00 | |
| xbar_stress_all_with_error | 454.440s | 15408.625us | 50 | 50 | 100.00 | |
| xbar_stress_with_reset | 100 | 100 | 100.00 | |||
| xbar_stress_all_with_rand_reset | 1098.580s | 30464.332us | 50 | 50 | 100.00 | |
| xbar_stress_all_with_reset_error | 590.600s | 18516.282us | 50 | 50 | 100.00 | |
| rom_e2e_smoke | 3 | 3 | 100.00 | |||
| rom_e2e_smoke | 3864.500s | 15016.578us | 3 | 3 | 100.00 | |
| rom_e2e_shutdown_output | 3 | 3 | 100.00 | |||
| rom_e2e_shutdown_output | 3671.400s | 30201.377us | 3 | 3 | 100.00 | |
| rom_e2e_shutdown_exception_c | 3 | 3 | 100.00 | |||
| rom_e2e_shutdown_exception_c | 3787.860s | 16500.636us | 3 | 3 | 100.00 | |
| rom_e2e_boot_policy_valid | 0 | 15 | 0.00 | |||
| rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 166.331s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 11.524s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 11.584s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 11.533s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 10.508s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 185.094s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 9.259s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 12.030s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 11.901s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 11.750s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 93.486s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 18.181s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 17.524s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 18.399s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 15.836s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always | 0 | 15 | 0.00 | |||
| rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 119.291s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 17.647s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 22.230s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 24.881s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 20.750s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 23.453s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 21.168s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 19.392s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 20.018s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 20.331s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 31.476s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 43.769s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 20.283s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 25.720s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 19.033s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init | 0 | 15 | 0.00 | |||
| rom_e2e_asm_init_test_unlocked0 | 107.722s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_asm_init_dev | 11.566s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_asm_init_prod | 11.577s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_asm_init_prod_end | 11.678s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_asm_init_rma | 13.213s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_keymgr_init | 7 | 9 | 77.78 | |||
| rom_e2e_keymgr_init_rom_ext_meas | 8060.870s | 29593.179us | 3 | 3 | 100.00 | |
| rom_e2e_keymgr_init_rom_ext_no_meas | 7787.950s | 29821.373us | 1 | 3 | 33.33 | |
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 7601.540s | 28863.785us | 3 | 3 | 100.00 | |
| rom_e2e_static_critical | 3 | 3 | 100.00 | |||
| rom_e2e_static_critical | 4092.500s | 17235.695us | 3 | 3 | 100.00 | |
| chip_sw_adc_ctrl_debug_cable_irq | 0 | 3 | 0.00 | |||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 3600.162s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 0 | 3 | 0.00 | |||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 3600.162s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_aes_enc | 6 | 6 | 100.00 | |||
| chip_sw_aes_enc | 283.230s | 3302.589us | 3 | 3 | 100.00 | |
| chip_sw_aes_enc_jitter_en | 232.320s | 2471.461us | 3 | 3 | 100.00 | |
| chip_sw_aes_entropy | 3 | 3 | 100.00 | |||
| chip_sw_aes_entropy | 226.170s | 2592.874us | 3 | 3 | 100.00 | |
| chip_sw_aes_idle | 3 | 3 | 100.00 | |||
| chip_sw_aes_idle | 240.260s | 3381.990us | 3 | 3 | 100.00 | |
| chip_sw_aes_sideload | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_sideload_aes | 2116.860s | 12370.998us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_alerts | 0 | 3 | 0.00 | |||
| chip_sw_alert_test | 269.400s | 3791.276us | 0 | 3 | 0.00 | |
| chip_sw_alert_handler_escalations | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_escalation | 527.560s | 6348.478us | 3 | 3 | 100.00 | |
| chip_sw_all_escalation_resets | 87 | 100 | 87.00 | |||
| chip_sw_all_escalation_resets | 644.470s | 6039.779us | 87 | 100 | 87.00 | |
| chip_sw_alert_handler_irqs | 9 | 9 | 100.00 | |||
| chip_plic_all_irqs_0 | 754.280s | 5132.674us | 3 | 3 | 100.00 | |
| chip_plic_all_irqs_10 | 354.070s | 3849.370us | 3 | 3 | 100.00 | |
| chip_plic_all_irqs_20 | 506.000s | 4639.776us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_entropy | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_entropy | 345.100s | 3851.609us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_crashdump | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_alert_info | 1477.280s | 11274.033us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_ping_timeout | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_ping_timeout | 452.250s | 5326.839us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 0 | 90 | 0.00 | |||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 267.970s | 3213.671us | 0 | 90 | 0.00 | |
| chip_sw_alert_handler_lpg_sleep_mode_pings | 0 | 3 | 0.00 | |||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 14400.164s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_alert_handler_lpg_clock_off | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_lpg_clkoff | 1449.240s | 7703.627us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_lpg_reset_toggle | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_lpg_reset_toggle | 1178.570s | 7218.045us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_ping_ok | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_ping_ok | 1052.480s | 8018.679us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 13755.640s | 255901.783us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_wakeup_irq | 3 | 3 | 100.00 | |||
| chip_sw_aon_timer_irq | 391.910s | 4683.996us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_sleep_wakeup | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_smoketest | 329.260s | 6259.162us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_wdog_bark_irq | 3 | 3 | 100.00 | |||
| chip_sw_aon_timer_irq | 391.910s | 4683.996us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_wdog_bite_reset | 1 | 3 | 33.33 | |||
| chip_sw_aon_timer_wdog_bite_reset | 693.420s | 7517.776us | 1 | 3 | 33.33 | |
| chip_sw_aon_timer_sleep_wdog_bite_reset | 1 | 3 | 33.33 | |||
| chip_sw_aon_timer_wdog_bite_reset | 693.420s | 7517.776us | 1 | 3 | 33.33 | |
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 5 | 5 | 100.00 | |||
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 481.990s | 7163.725us | 5 | 5 | 100.00 | |
| chip_sw_aon_timer_wdog_lc_escalate | 3 | 3 | 100.00 | |||
| chip_sw_aon_timer_wdog_lc_escalate | 546.360s | 6201.810us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_idle_trans | 12 | 12 | 100.00 | |||
| chip_sw_otbn_randomness | 787.880s | 6047.154us | 3 | 3 | 100.00 | |
| chip_sw_aes_idle | 240.260s | 3381.990us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_idle | 222.820s | 3604.390us | 3 | 3 | 100.00 | |
| chip_sw_kmac_idle | 210.030s | 3081.512us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_trans | 12 | 12 | 100.00 | |||
| chip_sw_clkmgr_off_aes_trans | 431.230s | 4284.572us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_hmac_trans | 453.460s | 5228.762us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_kmac_trans | 390.400s | 4074.344us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_otbn_trans | 468.820s | 5915.859us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_peri | 3 | 3 | 100.00 | |||
| chip_sw_clkmgr_off_peri | 1167.820s | 10513.945us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_div | 21 | 21 | 100.00 | |||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 545.810s | 4338.900us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 506.450s | 4353.851us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 488.470s | 4059.926us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 523.930s | 4539.412us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 520.130s | 4103.002us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 556.210s | 4968.582us | 3 | 3 | 100.00 | |
| chip_sw_ast_clk_outputs | 878.860s | 8234.277us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_lc | 3 | 3 | 100.00 | |||
| chip_sw_clkmgr_external_clk_src_for_lc | 706.640s | 11540.532us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw | 6 | 6 | 100.00 | |||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 488.470s | 4059.926us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 523.930s | 4539.412us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_jitter | 30 | 30 | 100.00 | |||
| chip_sw_flash_ctrl_ops_jitter_en | 511.300s | 4064.858us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_access_jitter_en | 806.670s | 6134.225us | 3 | 3 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 5004.400s | 19166.932us | 3 | 3 | 100.00 | |
| chip_sw_aes_enc_jitter_en | 232.320s | 2471.461us | 3 | 3 | 100.00 | |
| chip_sw_edn_entropy_reqs_jitter | 998.490s | 7711.046us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_jitter_en | 251.720s | 3562.638us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation_jitter_en | 2284.930s | 12101.103us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 270.240s | 3160.523us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 567.030s | 5850.868us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_jitter | 177.380s | 2345.385us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_extended_range | 32 | 33 | 96.97 | |||
| chip_sw_clkmgr_jitter_reduced_freq | 210.910s | 3277.223us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 481.410s | 5135.503us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 889.520s | 8086.064us | 3 | 3 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 4910.010s | 25221.003us | 3 | 3 | 100.00 | |
| chip_sw_aes_enc_jitter_en_reduced_freq | 222.950s | 3328.250us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_jitter_en_reduced_freq | 219.440s | 3531.853us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 1410.360s | 11954.570us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 244.210s | 3603.430us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 464.740s | 5257.879us | 3 | 3 | 100.00 | |
| chip_sw_flash_init_reduced_freq | 1836.380s | 27183.418us | 3 | 3 | 100.00 | |
| chip_sw_csrng_edn_concurrency_reduced_freq | 28800.159s | 0.000us | 2 | 3 | 66.67 | |
| chip_sw_clkmgr_deep_sleep_frequency | 3 | 3 | 100.00 | |||
| chip_sw_ast_clk_outputs | 878.860s | 8234.277us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_sleep_frequency | 3 | 3 | 100.00 | |||
| chip_sw_clkmgr_sleep_frequency | 518.470s | 4314.775us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_reset_frequency | 3 | 3 | 100.00 | |||
| chip_sw_clkmgr_reset_frequency | 356.260s | 3893.639us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_escalation_reset | 87 | 100 | 87.00 | |||
| chip_sw_all_escalation_resets | 644.470s | 6039.779us | 87 | 100 | 87.00 | |
| chip_sw_clkmgr_alert_handler_clock_enables | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_lpg_clkoff | 1449.240s | 7703.627us | 3 | 3 | 100.00 | |
| chip_sw_csrng_edn_cmd | 3 | 3 | 100.00 | |||
| chip_sw_entropy_src_csrng | 3055.720s | 24516.683us | 3 | 3 | 100.00 | |
| chip_sw_csrng_fuse_en_sw_app_read | 1 | 3 | 33.33 | |||
| chip_sw_csrng_fuse_en_sw_app_read_test | 346.600s | 4583.089us | 1 | 3 | 33.33 | |
| chip_sw_csrng_lc_hw_debug_en | 3 | 3 | 100.00 | |||
| chip_sw_csrng_lc_hw_debug_en_test | 664.620s | 8440.187us | 3 | 3 | 100.00 | |
| chip_sw_csrng_known_answer_tests | 3 | 3 | 100.00 | |||
| chip_sw_csrng_kat_test | 241.300s | 2970.792us | 3 | 3 | 100.00 | |
| chip_sw_edn_entropy_reqs | 16 | 16 | 100.00 | |||
| chip_sw_csrng_edn_concurrency | 5364.350s | 22194.617us | 10 | 10 | 100.00 | |
| chip_sw_entropy_src_ast_rng_req | 265.500s | 3603.737us | 3 | 3 | 100.00 | |
| chip_sw_edn_entropy_reqs | 957.040s | 7614.485us | 3 | 3 | 100.00 | |
| chip_sw_entropy_src_ast_rng_req | 3 | 3 | 100.00 | |||
| chip_sw_entropy_src_ast_rng_req | 265.500s | 3603.737us | 3 | 3 | 100.00 | |
| chip_sw_entropy_src_csrng | 3 | 3 | 100.00 | |||
| chip_sw_entropy_src_csrng | 3055.720s | 24516.683us | 3 | 3 | 100.00 | |
| chip_sw_entropy_src_known_answer_tests | 3 | 3 | 100.00 | |||
| chip_sw_entropy_src_kat_test | 189.730s | 3164.801us | 3 | 3 | 100.00 | |
| chip_sw_flash_init | 3 | 3 | 100.00 | |||
| chip_sw_flash_init | 1774.730s | 23440.415us | 3 | 3 | 100.00 | |
| chip_sw_flash_host_access | 6 | 6 | 100.00 | |||
| chip_sw_flash_ctrl_access | 781.560s | 5934.510us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_access_jitter_en | 806.670s | 6134.225us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_ops | 6 | 6 | 100.00 | |||
| chip_sw_flash_ctrl_ops | 479.280s | 3999.984us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_ops_jitter_en | 511.300s | 4064.858us | 3 | 3 | 100.00 | |
| chip_sw_flash_rma_unlocked | 3 | 3 | 100.00 | |||
| chip_sw_flash_rma_unlocked | 4948.390s | 44351.373us | 3 | 3 | 100.00 | |
| chip_sw_flash_scramble | 3 | 3 | 100.00 | |||
| chip_sw_flash_init | 1774.730s | 23440.415us | 3 | 3 | 100.00 | |
| chip_sw_flash_idle_low_power | 3 | 3 | 100.00 | |||
| chip_sw_flash_ctrl_idle_low_power | 326.070s | 4063.609us | 3 | 3 | 100.00 | |
| chip_sw_flash_keymgr_seeds | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_key_derivation | 2186.190s | 13085.639us | 3 | 3 | 100.00 | |
| chip_sw_flash_lc_creator_seed_sw_rw_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 200.450s | 3070.560us | 0 | 3 | 0.00 | |
| chip_sw_flash_creator_seed_wipe_on_rma | 3 | 3 | 100.00 | |||
| chip_sw_flash_rma_unlocked | 4948.390s | 44351.373us | 3 | 3 | 100.00 | |
| chip_sw_flash_lc_owner_seed_sw_rw_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 200.450s | 3070.560us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_iso_part_sw_rd_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 200.450s | 3070.560us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_iso_part_sw_wr_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 200.450s | 3070.560us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_seed_hw_rd_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 200.450s | 3070.560us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_escalate_en | 87 | 100 | 87.00 | |||
| chip_sw_all_escalation_resets | 644.470s | 6039.779us | 87 | 100 | 87.00 | |
| chip_sw_flash_prim_tl_access | 3 | 3 | 100.00 | |||
| chip_prim_tl_access | 406.710s | 12431.550us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_clock_freqs | 3 | 3 | 100.00 | |||
| chip_sw_flash_ctrl_clock_freqs | 755.730s | 5348.167us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_escalation_reset | 3 | 3 | 100.00 | |||
| chip_sw_flash_crash_alert | 617.600s | 5150.719us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_write_clear | 3 | 3 | 100.00 | |||
| chip_sw_flash_crash_alert | 617.600s | 5150.719us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc | 6 | 6 | 100.00 | |||
| chip_sw_hmac_enc | 257.110s | 3819.111us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_jitter_en | 251.720s | 3562.638us | 3 | 3 | 100.00 | |
| chip_sw_hmac_idle | 3 | 3 | 100.00 | |||
| chip_sw_hmac_enc_idle | 222.820s | 3604.390us | 3 | 3 | 100.00 | |
| chip_sw_hmac_all_configurations | 3 | 3 | 100.00 | |||
| chip_sw_hmac_oneshot | 1367.940s | 8069.294us | 3 | 3 | 100.00 | |
| chip_sw_hmac_multistream_mode | 3 | 3 | 100.00 | |||
| chip_sw_hmac_multistream | 980.780s | 5886.176us | 3 | 3 | 100.00 | |
| chip_sw_i2c_host_tx_rx | 9 | 9 | 100.00 | |||
| chip_sw_i2c_host_tx_rx | 509.850s | 4647.177us | 3 | 3 | 100.00 | |
| chip_sw_i2c_host_tx_rx_idx1 | 580.150s | 5227.193us | 3 | 3 | 100.00 | |
| chip_sw_i2c_host_tx_rx_idx2 | 547.690s | 5555.115us | 3 | 3 | 100.00 | |
| chip_sw_i2c_device_tx_rx | 3 | 3 | 100.00 | |||
| chip_sw_i2c_device_tx_rx | 380.000s | 3383.795us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation | 6 | 6 | 100.00 | |||
| chip_sw_keymgr_key_derivation | 2186.190s | 13085.639us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation_jitter_en | 2284.930s | 12101.103us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_sideload_kmac | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_sideload_kmac | 1863.800s | 11250.164us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_sideload_aes | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_sideload_aes | 2116.860s | 12370.998us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_sideload_otbn | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_sideload_otbn | 3757.040s | 15012.032us | 3 | 3 | 100.00 | |
| chip_sw_kmac_enc | 9 | 9 | 100.00 | |||
| chip_sw_kmac_mode_cshake | 213.550s | 2781.703us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac | 242.930s | 2794.695us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 270.240s | 3160.523us | 3 | 3 | 100.00 | |
| chip_sw_kmac_app_keymgr | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_key_derivation | 2186.190s | 13085.639us | 3 | 3 | 100.00 | |
| chip_sw_kmac_app_lc | 15 | 15 | 100.00 | |||
| chip_sw_lc_ctrl_transition | 858.560s | 10375.364us | 15 | 15 | 100.00 | |
| chip_sw_kmac_app_rom | 3 | 3 | 100.00 | |||
| chip_sw_kmac_app_rom | 247.880s | 3090.769us | 3 | 3 | 100.00 | |
| chip_sw_kmac_entropy | 3 | 3 | 100.00 | |||
| chip_sw_kmac_entropy | 914.810s | 6364.602us | 3 | 3 | 100.00 | |
| chip_sw_kmac_idle | 3 | 3 | 100.00 | |||
| chip_sw_kmac_idle | 210.030s | 3081.512us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_alert_handler_escalation | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_escalation | 527.560s | 6348.478us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_jtag_access | 15 | 15 | 100.00 | |||
| chip_tap_straps_dev | 1189.180s | 13885.673us | 5 | 5 | 100.00 | |
| chip_tap_straps_rma | 554.330s | 6903.002us | 5 | 5 | 100.00 | |
| chip_tap_straps_prod | 1510.170s | 17767.199us | 5 | 5 | 100.00 | |
| chip_sw_lc_ctrl_otp_hw_cfg0 | 3 | 3 | 100.00 | |||
| chip_sw_lc_ctrl_otp_hw_cfg0 | 212.830s | 2627.515us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_init | 15 | 15 | 100.00 | |||
| chip_sw_lc_ctrl_transition | 858.560s | 10375.364us | 15 | 15 | 100.00 | |
| chip_sw_lc_ctrl_transitions | 15 | 15 | 100.00 | |||
| chip_sw_lc_ctrl_transition | 858.560s | 10375.364us | 15 | 15 | 100.00 | |
| chip_sw_lc_ctrl_kmac_req | 15 | 15 | 100.00 | |||
| chip_sw_lc_ctrl_transition | 858.560s | 10375.364us | 15 | 15 | 100.00 | |
| chip_sw_lc_ctrl_key_div | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_key_derivation_prod | 2220.070s | 12836.269us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_broadcast | 75 | 84 | 89.29 | |||
| chip_sw_flash_ctrl_lc_rw_en | 200.450s | 3070.560us | 0 | 3 | 0.00 | |
| chip_sw_flash_rma_unlocked | 4948.390s | 44351.373us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 297.150s | 3703.777us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_dev | 745.650s | 8070.607us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_prod | 624.330s | 6596.707us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_rma | 684.450s | 7348.580us | 0 | 3 | 0.00 | |
| chip_sw_lc_ctrl_transition | 858.560s | 10375.364us | 15 | 15 | 100.00 | |
| chip_sw_keymgr_key_derivation | 2186.190s | 13085.639us | 3 | 3 | 100.00 | |
| chip_sw_rom_ctrl_integrity_check | 444.240s | 9888.327us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_execution_main | 617.470s | 9452.895us | 3 | 3 | 100.00 | |
| chip_prim_tl_access | 406.710s | 12431.550us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_lc | 706.640s | 11540.532us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 545.810s | 4338.900us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 506.450s | 4353.851us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 488.470s | 4059.926us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 523.930s | 4539.412us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 520.130s | 4103.002us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 556.210s | 4968.582us | 3 | 3 | 100.00 | |
| chip_tap_straps_dev | 1189.180s | 13885.673us | 5 | 5 | 100.00 | |
| chip_tap_straps_rma | 554.330s | 6903.002us | 5 | 5 | 100.00 | |
| chip_tap_straps_prod | 1510.170s | 17767.199us | 5 | 5 | 100.00 | |
| chip_rv_dm_lc_disabled | 208.990s | 5483.692us | 0 | 3 | 0.00 | |
| chip_lc_scrap | 5 | 6 | 83.33 | |||
| chip_sw_lc_ctrl_rma_to_scrap | 264.400s | 3919.527us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_raw_to_scrap | 97.470s | 3638.969us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_test_locked0_to_scrap | 119.230s | 2953.263us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_rand_to_scrap | 2454.170s | 26717.952us | 2 | 3 | 66.67 | |
| chip_lc_test_locked | 2 | 6 | 33.33 | |||
| chip_sw_lc_walkthrough_testunlocks | 2102.920s | 25485.677us | 2 | 3 | 66.67 | |
| chip_rv_dm_lc_disabled | 208.990s | 5483.692us | 0 | 3 | 0.00 | |
| chip_sw_lc_walkthrough | 5 | 15 | 33.33 | |||
| chip_sw_lc_walkthrough_dev | 846.470s | 8780.454us | 0 | 3 | 0.00 | |
| chip_sw_lc_walkthrough_prod | 962.880s | 11784.032us | 0 | 3 | 0.00 | |
| chip_sw_lc_walkthrough_prodend | 891.730s | 10965.184us | 3 | 3 | 100.00 | |
| chip_sw_lc_walkthrough_rma | 574.630s | 7643.111us | 0 | 3 | 0.00 | |
| chip_sw_lc_walkthrough_testunlocks | 2102.920s | 25485.677us | 2 | 3 | 66.67 | |
| chip_sw_lc_ctrl_volatile_raw_unlock | 6 | 9 | 66.67 | |||
| chip_sw_lc_ctrl_volatile_raw_unlock | 110.200s | 2357.166us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 85.300s | 2720.776us | 3 | 3 | 100.00 | |
| rom_volatile_raw_unlock | 114.282s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otbn_op | 6 | 6 | 100.00 | |||
| chip_sw_otbn_ecdsa_op_irq | 4912.480s | 17868.079us | 3 | 3 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 5004.400s | 19166.932us | 3 | 3 | 100.00 | |
| chip_sw_otbn_rnd_entropy | 3 | 3 | 100.00 | |||
| chip_sw_otbn_randomness | 787.880s | 6047.154us | 3 | 3 | 100.00 | |
| chip_sw_otbn_urnd_entropy | 3 | 3 | 100.00 | |||
| chip_sw_otbn_randomness | 787.880s | 6047.154us | 3 | 3 | 100.00 | |
| chip_sw_otbn_idle | 3 | 3 | 100.00 | |||
| chip_sw_otbn_randomness | 787.880s | 6047.154us | 3 | 3 | 100.00 | |
| chip_sw_otbn_mem_scramble | 3 | 3 | 100.00 | |||
| chip_sw_otbn_mem_scramble | 402.130s | 3455.683us | 3 | 3 | 100.00 | |
| chip_otp_ctrl_init | 15 | 15 | 100.00 | |||
| chip_sw_lc_ctrl_transition | 858.560s | 10375.364us | 15 | 15 | 100.00 | |
| chip_sw_otp_ctrl_keys | 15 | 15 | 100.00 | |||
| chip_sw_flash_init | 1774.730s | 23440.415us | 3 | 3 | 100.00 | |
| chip_sw_otbn_mem_scramble | 402.130s | 3455.683us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation | 2186.190s | 13085.639us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access | 601.100s | 4858.778us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_icache_invalidate | 248.470s | 3046.178us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_entropy | 15 | 15 | 100.00 | |||
| chip_sw_flash_init | 1774.730s | 23440.415us | 3 | 3 | 100.00 | |
| chip_sw_otbn_mem_scramble | 402.130s | 3455.683us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation | 2186.190s | 13085.639us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access | 601.100s | 4858.778us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_icache_invalidate | 248.470s | 3046.178us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_program | 15 | 15 | 100.00 | |||
| chip_sw_lc_ctrl_transition | 858.560s | 10375.364us | 15 | 15 | 100.00 | |
| chip_sw_otp_ctrl_program_error | 3 | 3 | 100.00 | |||
| chip_sw_lc_ctrl_program_error | 522.810s | 5270.551us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_hw_cfg0 | 3 | 3 | 100.00 | |||
| chip_sw_lc_ctrl_otp_hw_cfg0 | 212.830s | 2627.515us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals | 27 | 30 | 90.00 | |||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 297.150s | 3703.777us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_dev | 745.650s | 8070.607us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_prod | 624.330s | 6596.707us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_rma | 684.450s | 7348.580us | 0 | 3 | 0.00 | |
| chip_sw_lc_ctrl_transition | 858.560s | 10375.364us | 15 | 15 | 100.00 | |
| chip_prim_tl_access | 406.710s | 12431.550us | 3 | 3 | 100.00 | |
| chip_sw_otp_prim_tl_access | 3 | 3 | 100.00 | |||
| chip_prim_tl_access | 406.710s | 12431.550us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_dai_lock | 1 | 1 | 100.00 | |||
| chip_sw_otp_ctrl_dai_lock | 1127.790s | 7999.005us | 1 | 1 | 100.00 | |
| chip_sw_pwrmgr_external_full_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_full_aon_reset | 270.800s | 6584.629us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_random_sleep_all_wake_ups | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_random_sleep_all_wake_ups | 1495.500s | 29058.990us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_normal_sleep_all_wake_ups | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_normal_sleep_all_wake_ups | 375.350s | 7676.348us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_deep_sleep_por_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_deep_sleep_por_reset | 453.590s | 7687.642us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_normal_sleep_por_reset | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_normal_sleep_por_reset | 668.520s | 7464.993us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_deep_sleep_all_wake_ups | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_deep_sleep_all_wake_ups | 1310.640s | 22494.179us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 2 | 6 | 33.33 | |||
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 1065.650s | 13101.780us | 1 | 3 | 33.33 | |
| chip_sw_aon_timer_wdog_bite_reset | 693.420s | 7517.776us | 1 | 3 | 33.33 | |
| chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 1233.390s | 10089.623us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_wdog_reset | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_wdog_reset | 473.800s | 5652.671us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_aon_power_glitch_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_full_aon_reset | 270.800s | 6584.629us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_main_power_glitch_reset | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_main_power_glitch_reset | 461.700s | 4627.977us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 1507.650s | 16447.492us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 349.510s | 7543.613us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_sleep_power_glitch_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_sleep_power_glitch_reset | 223.170s | 2955.756us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 999.270s | 14011.497us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_sysrst_ctrl_reset | 6 | 6 | 100.00 | |||
| chip_sw_pwrmgr_sysrst_ctrl_reset | 1119.590s | 9236.238us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_all_reset_reqs | 1572.130s | 12112.376us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_b2b_sleep_reset_req | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_b2b_sleep_reset_req | 2383.750s | 35566.361us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_sleep_disabled | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_sleep_disabled | 270.420s | 3698.431us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_escalation_reset | 87 | 100 | 87.00 | |||
| chip_sw_all_escalation_resets | 644.470s | 6039.779us | 87 | 100 | 87.00 | |
| chip_sw_rom_access | 3 | 3 | 100.00 | |||
| chip_sw_rom_ctrl_integrity_check | 444.240s | 9888.327us | 3 | 3 | 100.00 | |
| chip_sw_rom_ctrl_integrity_check | 3 | 3 | 100.00 | |||
| chip_sw_rom_ctrl_integrity_check | 444.240s | 9888.327us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_non_sys_reset_info | 9 | 12 | 75.00 | |||
| chip_sw_pwrmgr_all_reset_reqs | 1572.130s | 12112.376us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 999.270s | 14011.497us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_wdog_reset | 473.800s | 5652.671us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_smoketest | 329.260s | 6259.162us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_sys_reset_info | 3 | 3 | 100.00 | |||
| chip_rv_dm_ndm_reset_req | 408.850s | 4833.110us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_cpu_info | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_cpu_info | 557.370s | 6828.966us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_sw_req_reset | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_sw_req | 422.730s | 4795.632us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_alert_info | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_alert_info | 1477.280s | 11274.033us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_sw_rst | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_sw_rst | 248.700s | 3053.615us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_escalation_reset | 87 | 100 | 87.00 | |||
| chip_sw_all_escalation_resets | 644.470s | 6039.779us | 87 | 100 | 87.00 | |
| chip_sw_rstmgr_alert_handler_reset_enables | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_lpg_reset_toggle | 1178.570s | 7218.045us | 3 | 3 | 100.00 | |
| chip_sw_nmi_irq | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_nmi_irq | 638.140s | 4549.641us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_rnd | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_rnd | 652.490s | 4275.918us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_address_translation | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_address_translation | 264.340s | 3518.897us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_icache_scrambled_access | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_icache_invalidate | 248.470s | 3046.178us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_fault_dump | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_cpu_info | 557.370s | 6828.966us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_double_fault | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_cpu_info | 557.370s | 6828.966us | 3 | 3 | 100.00 | |
| chip_jtag_csr_rw | 3 | 3 | 100.00 | |||
| chip_jtag_csr_rw | 1721.230s | 18747.621us | 3 | 3 | 100.00 | |
| chip_jtag_mem_access | 3 | 3 | 100.00 | |||
| chip_jtag_mem_access | 1307.480s | 13448.172us | 3 | 3 | 100.00 | |
| chip_rv_dm_ndm_reset_req | 3 | 3 | 100.00 | |||
| chip_rv_dm_ndm_reset_req | 408.850s | 4833.110us | 3 | 3 | 100.00 | |
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 0 | 3 | 0.00 | |||
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 293.870s | 3339.241us | 0 | 3 | 0.00 | |
| chip_rv_dm_access_after_wakeup | 3 | 3 | 100.00 | |||
| chip_sw_rv_dm_access_after_wakeup | 490.050s | 6661.032us | 3 | 3 | 100.00 | |
| chip_sw_rv_dm_jtag_tap_sel | 5 | 5 | 100.00 | |||
| chip_tap_straps_rma | 554.330s | 6903.002us | 5 | 5 | 100.00 | |
| chip_rv_dm_lc_disabled | 0 | 3 | 0.00 | |||
| chip_rv_dm_lc_disabled | 208.990s | 5483.692us | 0 | 3 | 0.00 | |
| chip_sw_plic_all_irqs | 9 | 9 | 100.00 | |||
| chip_plic_all_irqs_0 | 754.280s | 5132.674us | 3 | 3 | 100.00 | |
| chip_plic_all_irqs_10 | 354.070s | 3849.370us | 3 | 3 | 100.00 | |
| chip_plic_all_irqs_20 | 506.000s | 4639.776us | 3 | 3 | 100.00 | |
| chip_sw_plic_sw_irq | 3 | 3 | 100.00 | |||
| chip_sw_plic_sw_irq | 226.380s | 2844.332us | 3 | 3 | 100.00 | |
| chip_sw_timer | 3 | 3 | 100.00 | |||
| chip_sw_rv_timer_irq | 253.700s | 3307.458us | 3 | 3 | 100.00 | |
| chip_sw_spi_device_flash_mode | 3 | 3 | 100.00 | |||
| rom_e2e_smoke | 3864.500s | 15016.578us | 3 | 3 | 100.00 | |
| chip_sw_spi_device_pass_through | 3 | 3 | 100.00 | |||
| chip_sw_spi_device_pass_through | 518.980s | 6040.507us | 3 | 3 | 100.00 | |
| chip_sw_spi_device_pass_through_collision | 0 | 3 | 0.00 | |||
| chip_sw_spi_device_pass_through_collision | 313.630s | 3034.260us | 0 | 3 | 0.00 | |
| chip_sw_spi_device_tpm | 3 | 3 | 100.00 | |||
| chip_sw_spi_device_tpm | 310.280s | 4014.965us | 3 | 3 | 100.00 | |
| chip_sw_spi_host_tx_rx | 3 | 3 | 100.00 | |||
| chip_sw_spi_host_tx_rx | 277.030s | 3579.951us | 3 | 3 | 100.00 | |
| chip_sw_sram_scrambled_access | 6 | 6 | 100.00 | |||
| chip_sw_sram_ctrl_scrambled_access | 601.100s | 4858.778us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 567.030s | 5850.868us | 3 | 3 | 100.00 | |
| chip_sw_sleep_sram_ret_contents | 6 | 6 | 100.00 | |||
| chip_sw_sleep_sram_ret_contents_no_scramble | 632.720s | 8134.087us | 3 | 3 | 100.00 | |
| chip_sw_sleep_sram_ret_contents_scramble | 560.360s | 8008.362us | 3 | 3 | 100.00 | |
| chip_sw_sram_execution | 3 | 3 | 100.00 | |||
| chip_sw_sram_ctrl_execution_main | 617.470s | 9452.895us | 3 | 3 | 100.00 | |
| chip_sw_sram_lc_escalation | 93 | 106 | 87.74 | |||
| chip_sw_all_escalation_resets | 644.470s | 6039.779us | 87 | 100 | 87.00 | |
| chip_sw_data_integrity_escalation | 684.370s | 6459.827us | 6 | 6 | 100.00 | |
| chip_sw_sysrst_ctrl_reset | 6 | 6 | 100.00 | |||
| chip_sw_pwrmgr_sysrst_ctrl_reset | 1119.590s | 9236.238us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_reset | 1681.210s | 25298.744us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_inputs | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_inputs | 234.790s | 3744.651us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_outputs | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_outputs | 320.400s | 3798.892us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_in_irq | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_in_irq | 417.870s | 5418.084us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_sleep_wakeup | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_reset | 1681.210s | 25298.744us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_sleep_reset | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_reset | 1681.210s | 25298.744us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_ec_rst_l | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_ec_rst_l | 3187.620s | 20035.338us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_flash_wp_l | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_ec_rst_l | 3187.620s | 20035.338us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_ulp_z3_wakeup | 3 | 6 | 50.00 | |||
| chip_sw_sysrst_ctrl_ulp_z3_wakeup | 468.540s | 6727.814us | 3 | 3 | 100.00 | |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 3600.162s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_usbdev_vbus | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_vbus | 228.840s | 3071.510us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_pullup | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_pullup | 175.180s | 2835.804us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_aon_pullup | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_aon_pullup | 426.880s | 4517.708us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_setup_rx | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_setuprx | 387.150s | 4474.774us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_config_host | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_config_host | 1241.550s | 8516.027us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_pincfg | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_pincfg | 6924.410s | 31693.002us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_tx_rx | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_dpi | 2236.420s | 12622.301us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_toggle_restore | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_toggle_restore | 245.090s | 3073.714us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_aes_masking_off | 3 | 3 | 100.00 | |||
| chip_sw_aes_masking_off | 218.440s | 3409.007us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_lockstep_glitch | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_lockstep_glitch | 127.700s | 2920.111us | 3 | 3 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_coremark | 1 | 1 | 100.00 | |||
| chip_sw_coremark | 16634.220s | 71634.156us | 1 | 1 | 100.00 | |
| chip_sw_power_max_load | 3 | 3 | 100.00 | |||
| chip_sw_power_virus | 1500.960s | 6544.622us | 3 | 3 | 100.00 | |
| rom_e2e_debug | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_debug_test_unlocked0 | 303.090s | 4337.768us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_dev | 241.800s | 3326.784us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_rma | 244.620s | 4172.360us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_inject_test_unlocked0 | 19.030s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject_dev | 18.745s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject_rma | 18.715s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_self_hash | 0 | 3 | 0.00 | |||
| rom_e2e_self_hash | 86.712s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_jitter_cycle_measurements | 0 | 3 | 0.00 | |||
| chip_sw_clkmgr_jitter_frequency | 390.660s | 3251.602us | 0 | 3 | 0.00 | |
| chip_sw_edn_boot_mode | 3 | 3 | 100.00 | |||
| chip_sw_edn_boot_mode | 485.260s | 3235.771us | 3 | 3 | 100.00 | |
| chip_sw_edn_auto_mode | 3 | 3 | 100.00 | |||
| chip_sw_edn_auto_mode | 652.770s | 3612.500us | 3 | 3 | 100.00 | |
| chip_sw_edn_sw_mode | 3 | 3 | 100.00 | |||
| chip_sw_edn_sw_mode | 2069.150s | 11108.181us | 3 | 3 | 100.00 | |
| chip_sw_edn_kat | 3 | 3 | 100.00 | |||
| chip_sw_edn_kat | 328.520s | 2483.635us | 3 | 3 | 100.00 | |
| chip_sw_flash_memory_protection | 3 | 3 | 100.00 | |||
| chip_sw_flash_ctrl_mem_protection | 816.780s | 5790.186us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_vendor_test_csr_access | 3 | 3 | 100.00 | |||
| chip_sw_otp_ctrl_vendor_test_csr_access | 235.690s | 3413.940us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_escalation | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_escalation | 225.350s | 3132.630us | 0 | 1 | 0.00 | |
| chip_sw_sensor_ctrl_deep_sleep_wake_up | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 433.390s | 6889.714us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_usb_clk_disabled_when_active | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_usb_clk_disabled_when_active | 425.780s | 5012.606us | 3 | 3 | 100.00 | |
| chip_sw_all_resets | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_all_reset_reqs | 1572.130s | 12112.376us | 3 | 3 | 100.00 | |
| chip_rv_dm_perform_debug | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_debug_test_unlocked0 | 303.090s | 4337.768us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_dev | 241.800s | 3326.784us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_rma | 244.620s | 4172.360us | 0 | 1 | 0.00 | |
| chip_sw_rv_dm_access_after_hw_reset | 3 | 3 | 100.00 | |||
| chip_sw_rv_dm_access_after_escalation_reset | 503.350s | 6386.921us | 3 | 3 | 100.00 | |
| chip_sw_plic_alerts | 87 | 100 | 87.00 | |||
| chip_sw_all_escalation_resets | 644.470s | 6039.779us | 87 | 100 | 87.00 | |
| tick_configuration | 0 | 3 | 0.00 | |||
| chip_sw_rv_timer_systick_test | 7200.167s | 0.000us | 0 | 3 | 0.00 | |
| counter_wrap | 0 | 3 | 0.00 | |||
| chip_sw_rv_timer_systick_test | 7200.167s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_spi_device_output_when_disabled_or_sleeping | 3 | 3 | 100.00 | |||
| chip_sw_spi_device_pinmux_sleep_retention | 232.610s | 3730.204us | 3 | 3 | 100.00 | |
| chip_sw_uart_watermarks | 5 | 5 | 100.00 | |||
| chip_sw_uart_tx_rx | 525.490s | 5033.631us | 5 | 5 | 100.00 | |
| chip_sw_usbdev_stream | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_stream | 3911.520s | 19189.802us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 21 | 31 | 67.74 | |||
| chip_sival_flash_info_access | 280.590s | 3114.539us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 580.930s | 5857.531us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_rot_auth_config | 8.610s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_ecc_error_vendor_test | 268.270s | 3328.233us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_descrambling | 248.740s | 3482.917us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_lowpower_cancel | 344.320s | 3800.201us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_sleep_wake_5_bug | 11.059s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_ctrl_write_clear | 277.140s | 3125.374us | 3 | 3 | 100.00 | |
| ate_bootstrap_flash_erase | 800.590s | 10010.220us | 0 | 3 | 0.00 | |
| ate_bootstrap_one_frame | 9798.760s | 44876.169us | 3 | 3 | 100.00 | |
| ate_bootstrap_disjoint | 10800.167s | 0.000us | 0 | 3 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) | 90 test runs | |||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 60400947315658836470694371999431193518683962286783770162685129756661303606022 | 308 |
UVM_INFO @ 2855.764101 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 114538712035052849020818451471953813746236801136046267073233384595607510268322 | 308 |
UVM_INFO @ 2958.608940 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 39735591031318743960812566306614086122501324527152918625576269303146060347700 | 308 |
UVM_INFO @ 2959.851439 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 55261283510167462914568136347941992896546789802942452456870834469923781466396 | 308 |
UVM_INFO @ 3094.379337 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 27017009401446433111147639259199814545278701325877816736102105897936939154078 | 308 |
UVM_INFO @ 2640.772648 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 39388390743759060341039618793129857904117349301036731476101623002359775177854 | 308 |
UVM_INFO @ 2872.058725 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 52007861603007076031531515159568065384502663976740527209908888113829690872232 | 308 |
UVM_INFO @ 3374.959936 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 90364484704554538538927865978177583280966196471228261901201102111624928987041 | 308 |
UVM_INFO @ 3077.941816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 31807996404089881209219861155482212880569642669388884869290349783925065420124 | 308 |
UVM_INFO @ 3279.547758 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 61927341250551970395779262259882821084073489823416459715237428089306954740200 | 308 |
UVM_INFO @ 3405.977647 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 69964227592519558857103024688311363319138957059368570910270872867836543949818 | 308 |
UVM_INFO @ 3317.588424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 53120595232716671492787777881329569136158015034001742673232708165041977634858 | 308 |
UVM_INFO @ 2601.692108 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 30887947820123812605705964061695772735039075478857684163271976967497518001747 | 308 |
UVM_INFO @ 3255.552644 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 111031464153410670369338862100818731021090590960573387524329356943967759769031 | 308 |
UVM_INFO @ 2631.157778 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 81144610270931100368650806778495010510634732153182594086235733641328935915137 | 308 |
UVM_INFO @ 2609.823772 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 12619578461951736636511492110537326455293125065661297436675680159738337517411 | 308 |
UVM_INFO @ 2930.011965 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 61094674572317832251248120085233094091610151387656200727217573421274001158038 | 308 |
UVM_INFO @ 2786.562646 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 29124741121758266047793486863259462798686961897246155103339581445959047919116 | 308 |
UVM_INFO @ 3316.648212 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 99029786667851572893401642762049063893565126848004371815847697831717161551746 | 308 |
UVM_INFO @ 3526.285000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 60687934755649423499059862552628291020645028576817529360674929553290836809898 | 308 |
UVM_INFO @ 3022.390477 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 28292183501471175937502237959543192805426109148466807033207378194912025336073 | 308 |
UVM_INFO @ 2811.459816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 96964832181694443226369638722225709077601083880048244664032062891970451355159 | 308 |
UVM_INFO @ 3097.469932 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 91592196171360046863647174003972645673107726787853375844930438333943902102122 | 308 |
UVM_INFO @ 2365.148020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 64198242733684929306754007813719503988820018693641457897072388076919527478796 | 308 |
UVM_INFO @ 3095.690562 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 21242093172203125229732260932004637863370980862225238900215701831972805973141 | 308 |
UVM_INFO @ 3528.079020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 115389423500048088241691246776310831589392979689960871408508307985647347227070 | 308 |
UVM_INFO @ 2561.314691 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 58842733613517480937892056259883267461354451898782451357389551850887164769001 | 308 |
UVM_INFO @ 2919.313670 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 7151470351613318039158800687058166806352699774718118050567377854118763272668 | 308 |
UVM_INFO @ 3655.960376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 91155476926117290786291980866157966160824662005013043821037156246982768990663 | 308 |
UVM_INFO @ 3287.512532 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 86243323214315286272457134168287416878022436352376083370958443538188364245809 | 308 |
UVM_INFO @ 2739.820275 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 110954516557282319013129888282333499665642220178659408192689320746099638078367 | 308 |
UVM_INFO @ 3047.725320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 33854449545343394893731571420009481696230070827795020728658244038480415289766 | 308 |
UVM_INFO @ 2157.264985 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 113196779278674926197509341444904337559838643849455023949753610026576743445519 | 308 |
UVM_INFO @ 2723.574844 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 115492331086279056611847757744217049261673748221594474863548155674575690394450 | 308 |
UVM_INFO @ 2876.140988 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 114241035513467823810936717921427341399223872759857113032403164638772532845701 | 308 |
UVM_INFO @ 3093.603256 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 66065564839168847785572520798234787146638110914359750444097932748333200838621 | 308 |
UVM_INFO @ 2568.852915 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 46253124217493589113809062821594863513624937918164522770725494995971025517507 | 308 |
UVM_INFO @ 2739.325624 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 54358257783501162395839142815009230202617198813658144528880770498543487497379 | 308 |
UVM_INFO @ 2946.164424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 47192548093674967266066527945329650295575917014036986092864800461134020098956 | 308 |
UVM_INFO @ 3226.112657 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 98148678864232930126704950858740036428181975388020812608126393210638651554789 | 308 |
UVM_INFO @ 2731.859914 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 77740160127741697043671063910570383195959376704829862999132643865905746864558 | 308 |
UVM_INFO @ 2283.971950 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 65401953904783977727847586654677217955256110222688366928133877696101110557825 | 308 |
UVM_INFO @ 2851.816720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 104338469084955173496775235212518189029657605527685624433153674690074548943171 | 308 |
UVM_INFO @ 2694.719635 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 9145351064817265025994047233433006503684304479884740380789079775561402504015 | 308 |
UVM_INFO @ 3643.916230 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 14494652022080441383225429369398692830032462330472645073837028557844963952519 | 308 |
UVM_INFO @ 3213.671280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 26861778416131635982343597850211515121758568562605897213473274615829293977534 | 308 |
UVM_INFO @ 2469.297640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 101581179814632001762134814705898435714752385377300699114288774590712534722443 | 308 |
UVM_INFO @ 3360.201394 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 35945038859636609620469501521235614716425737589952323628991053259640235554174 | 308 |
UVM_INFO @ 3098.654944 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 66842518611165355360106414834200542489817956877685955075955365956454528341346 | 308 |
UVM_INFO @ 2672.378240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 88435454351794578474587478069306325123863359730856897111385297348826874827112 | 308 |
UVM_INFO @ 3532.321563 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 1323529898773794312992124041451658227161106823199265821124792799097481400295 | 308 |
UVM_INFO @ 2805.384460 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 30837230829404486128630786638071718875239607347294293646064424816858577047322 | 308 |
UVM_INFO @ 3400.442094 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 7572988357665269314780746781355035217823671546310989319319515904520208494766 | 308 |
UVM_INFO @ 2925.475405 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 36896404851803659835278910401397997008711542872327730570494576372320089007373 | 308 |
UVM_INFO @ 3051.412360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 2075454755884086431354379233700012508085549520773824965615300314518405430886 | 308 |
UVM_INFO @ 3007.581889 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 106621009478311761455831376370525316913295276993729031655062080377522096461474 | 308 |
UVM_INFO @ 3202.900060 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 8755550689663126117020388615221442609577899713092230426126330681268435036965 | 308 |
UVM_INFO @ 3079.777908 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 95066594085552974420677903031154941499414822612501299750133596426463087030377 | 308 |
UVM_INFO @ 2963.969448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 47180997114131877471206721437495807912347565438017128521132308689762568252673 | 308 |
UVM_INFO @ 2927.289966 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 98603787755708602650112336850494433260301776989041151276487426812993188888993 | 308 |
UVM_INFO @ 3518.293734 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 81184617675100533642451066091516218731538675176829758221477610705606935900900 | 308 |
UVM_INFO @ 2916.889472 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 114603171951359949222703798079353820271679313768694647850300135713090692233702 | 308 |
UVM_INFO @ 2663.853814 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 67325915610168686112529417051714861950957245218600871436628562467248807142301 | 308 |
UVM_INFO @ 3101.807998 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 84005533979036340615865212916968966331677958201794110922161695822215160719428 | 308 |
UVM_INFO @ 3113.515088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 62287602313294266755244596756540340420204211361015573190885720307619812576125 | 308 |
UVM_INFO @ 2670.232552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 109311506681815960072303611720032837316581626219155561110786054713509675483465 | 308 |
UVM_INFO @ 3104.470484 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 81351735883778001510477644473332057851392651486604154377356557880640596947802 | 308 |
UVM_INFO @ 3290.138250 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 1697029827398451375653062470204043759362397256876444587030294926970405717531 | 308 |
UVM_INFO @ 2979.815105 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 76371374024087098365585932128107282487094767818183397374907468267517532908454 | 308 |
UVM_INFO @ 2609.405078 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 88678188396628225708612889269443481026185218295866547307026148553323155930947 | 308 |
UVM_INFO @ 2719.797668 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 80158086367838871555479434868226386986954705728607293035321015201325686426378 | 308 |
UVM_INFO @ 2496.115628 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 94972060934563732129286097748187452338151754063850004068256169151244267162464 | 308 |
UVM_INFO @ 2544.529878 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 38509270740174026326483753239039714791662220903014830461680309146892274498647 | 308 |
UVM_INFO @ 3080.032156 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 64552373752113917292541959901828027246603467251589799284537765904016091935034 | 308 |
UVM_INFO @ 3356.584534 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 65640032641031565856742717192372911306263618460150591681085835943717302015344 | 308 |
UVM_INFO @ 2699.835250 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 73984463788192440041949350832483377441363603115371124930992508568484177532479 | 308 |
UVM_INFO @ 2915.225435 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 114003367582749130599232326107284202117556682540133732077394410331861237696049 | 308 |
UVM_INFO @ 2673.608008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 51381029666327911379322928005760455247311111186827189828262546833323780634906 | 308 |
UVM_INFO @ 3224.490248 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 64463357062133903666343801956492144177708624461032860994387125848531031595927 | 308 |
UVM_INFO @ 2452.191340 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 45852081254889269972097482812820873792559110665664685307788323401048017303414 | 308 |
UVM_INFO @ 2641.933080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 99530596940711969404421094590677512514828688070596971166124952307459404802325 | 308 |
UVM_INFO @ 2904.332617 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 60579371498624936599428369680022274254868330677270872565829467160751039959721 | 308 |
UVM_INFO @ 3027.530766 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 92040054208613154126120876807283776565584019002729358207414691435346773268344 | 308 |
UVM_INFO @ 2957.189492 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 60683630405525593974092410476965198352202887444739137464473606348484902831454 | 308 |
UVM_INFO @ 3017.446731 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 27151589545587358968307502504361563680855213679985912072552777753753551236036 | 308 |
UVM_INFO @ 2840.976470 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 91587556566251016501549969531583171920052368084412598973418791833565082411926 | 308 |
UVM_INFO @ 3072.358897 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 4145376902816235767374035207638418352371460357883283886309669647925078795149 | 308 |
UVM_INFO @ 2950.397514 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 65855154194520628959800573385422997214329114797533423132991737968227406352216 | 308 |
UVM_INFO @ 3082.031547 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 104475785129660372453333415882150004376226524527619148953143513297778568684857 | 308 |
UVM_INFO @ 3041.772204 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 80224713182216869770158154881300716029318213406810994603364119265082716941435 | 308 |
UVM_INFO @ 2874.748206 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] | 60 test runs | |||
| chip_sw_pwrmgr_sleep_wake_5_bug | 55614540328788100992778719231119360673799210738289208694908928965053730620154 | None |
---- STDERR ----
Another command (pid=3080289) is running. Waiting for it to complete on the server (server_pid=264734)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 50389252725262763035030782486810383107218701285643627761535191869254910194491 | None |
Another command (pid=273542) is running. Waiting for it to complete on the server (server_pid=264734)...
Another command (pid=280869) is running. Waiting for it to complete on the server (server_pid=264734)...
Another command (pid=275174) is running. Waiting for it to complete on the server (server_pid=264734)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 51592991347872151431865811962519752974951601977285598798398796644147556032405 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 99222698597857480076586085576671597019579546681893178006560233414343981916052 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 3677745832152294798161170245633075469061768910034965768912281803266537974453 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 23292548715752848710183718230496679746801717313876960299321187408453369451974 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 77278212158764329798439234593612260329785984522982240721830871371084928354138 | None |
Another command (pid=296808) is running. Waiting for it to complete on the server (server_pid=264734)...
Another command (pid=272795) is running. Waiting for it to complete on the server (server_pid=264734)...
Another command (pid=272363) is running. Waiting for it to complete on the server (server_pid=264734)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 15215258607373167559756539216708348519320024715400897896215100447240616803260 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 82846559542197463998535359295707563648242275108898704042403317483017422950328 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 34161832245862045967364952349516900909372684241485617335691967065273794173315 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 68609528451146670824986061338086674647670348734174615680665799189382258387387 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 15012679523246385902245917589269560118245125790398165045555756303877320249631 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 39520742215261295319076225368663300420321423132724633550168674938594262194211 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 109840635823581331353293941254131708900525022447266282560886010678174237945054 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 115044919026951478553240340227602556027439584065854215393682704080109511022420 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 37063138186091678606776019800763567076490061479075756070593716613851881459048 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 105349015713468326411637015246590253508425534186077109683641918744123520636663 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 67684230358645931486503160653206906376287086884506571171944971027311818222138 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 13308193064351528659268440985216373823713507848714729885388809221561856188996 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 60501675024194394789730576167461093532656275129197516556992614070724824980940 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 1294502592987456923470177753129960960493525354123100705569207214939788831934 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 63470813600793640684411038021570520382798283452277388370138819561664515200661 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 42646847478381721462887409835485486066378088582657141692788458276067477517458 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 51193731885561816136790404442688900923204040078058532671596054860400624785191 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 86735622954034166539396096196289607959065294246130143410303294955588479064202 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 104218516375905988019288160113477528532624226102477816652032515998405749979345 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 84694130060691388055358259663591694988346138923188394481677257240881155727861 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 43915856724206536737607838274716922847750853994275651267700811315896024524231 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 89317041100970421322276154691056970238558220392515660471741251740886397905908 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 70827557314190073224760252368406893902334381397026027316513255832256939368718 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 53210112295863161702164021145934567870223350652899122569336905726583706052901 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_test_unlocked0 | 81516448321264515161005767307122863905113636589618661058501900567004343741872 | None |
Another command (pid=265180) is running. Waiting for it to complete on the server (server_pid=264734)...
Another command (pid=264787) is running. Waiting for it to complete on the server (server_pid=264734)...
Another command (pid=268093) is running. Waiting for it to complete on the server (server_pid=264734)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_dev | 58972783124364343557059391195203827664446495191944245410788128527845619795464 | None |
---- STDERR ----
Another command (pid=401964) is running. Waiting for it to complete on the server (server_pid=264734)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod | 60397056698154289351481798698683237335207072431389307821166799762771561743359 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod_end | 43262267176117780308460176321920913823497077683066377624112629788659840456189 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_rma | 97588057414741734647394193392755375943496288678818082746770613647357937004411 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_inject_test_unlocked0 | 40065476749744994824070358458577595397210622433332302767940941832677962157821 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/examples/sram_program:sram_program' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_inject_dev | 88665004957596531521893288414021251604102715360129028853339181961737481590477 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/examples/sram_program:sram_program' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_inject_rma | 23066361500756507496218898697536913146985294440854089057137508616322343885761 | None |
File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
fail("Bitstream cache not initialized properly.")
Error in fail: Bitstream cache not initialized properly.
ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
ERROR: Analysis of target '//sw/device/examples/sram_program:sram_program' failed; build aborted: Analysis failed
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_volatile_raw_unlock | 101688734402139651884584026099812591640776541591020946065133060979700046065543 | None |
Another command (pid=273807) is running. Waiting for it to complete on the server (server_pid=264734)...
Another command (pid=294464) is running. Waiting for it to complete on the server (server_pid=264734)...
Another command (pid=295193) is running. Waiting for it to complete on the server (server_pid=264734)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_raw_unlock | 67958431209182439379672629802212341651320960660702211798692640824192041244327 | None |
Another command (pid=265071) is running. Waiting for it to complete on the server (server_pid=264734)...
Another command (pid=267487) is running. Waiting for it to complete on the server (server_pid=264734)...
Another command (pid=271358) is running. Waiting for it to complete on the server (server_pid=264734)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_self_hash | 104300252799385344753975033786342335045125398668593398997557463682551318692812 | None |
Another command (pid=268093) is running. Waiting for it to complete on the server (server_pid=264734)...
Another command (pid=265071) is running. Waiting for it to complete on the server (server_pid=264734)...
Another command (pid=267487) is running. Waiting for it to complete on the server (server_pid=264734)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_sleep_wake_5_bug | 41808255464964538955238886495668582417357738237805725554341703472585327174328 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_test_unlocked0 | 109428265983069528347300869636966509496246472777633199737029913377503610916724 | None |
---- STDERR ----
Another command (pid=273542) is running. Waiting for it to complete on the server (server_pid=264734)...
Another command (pid=275174) is running. Waiting for it to complete on the server (server_pid=264734)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_dev | 94745419614159170496346739956701773798185248401060778764713225022473878519384 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod | 79809702058530776060380193412405990268763106271426575071704333605725691850793 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod_end | 112798731093656167824161961211668489543133759775240398609518892637159055738565 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_rma | 13335029585208251734393627423747902046341655715825595699638945284523481671761 | None |
---- STDERR ----
Another command (pid=410799) is running. Waiting for it to complete on the server (server_pid=264734)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_volatile_raw_unlock | 48567461982676841513637414039179897479337212341804859726846388353586617509064 | None |
Another command (pid=301851) is running. Waiting for it to complete on the server (server_pid=264734)...
Another command (pid=301343) is running. Waiting for it to complete on the server (server_pid=264734)...
Another command (pid=306940) is running. Waiting for it to complete on the server (server_pid=264734)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_raw_unlock | 22540236397109950455142129353539096461166399384976532741116676269722275297767 | None |
Another command (pid=275174) is running. Waiting for it to complete on the server (server_pid=264734)...
Another command (pid=291734) is running. Waiting for it to complete on the server (server_pid=264734)...
Another command (pid=292723) is running. Waiting for it to complete on the server (server_pid=264734)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_self_hash | 99278777663022523926284711717049602368947979951116680283166408149182534051135 | None |
Waiting for it to complete...
Another command (pid=273542) is running. Waiting for it to complete on the server (server_pid=264734)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_sleep_wake_5_bug | 100692013152855411093317796506555528988888641435094818620122405362692426645441 | None |
---- STDERR ----
Another command (pid=758330) is running. Waiting for it to complete on the server (server_pid=264734)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_test_unlocked0 | 89440805811873542566320210427514995291156086084954100765990440977741490452036 | None |
Another command (pid=307783) is running. Waiting for it to complete on the server (server_pid=264734)...
Another command (pid=309833) is running. Waiting for it to complete on the server (server_pid=264734)...
Another command (pid=304287) is running. Waiting for it to complete on the server (server_pid=264734)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_dev | 62238028909715979367520308603521501198312304300782175879861845494843438759320 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod | 99825354416964346975572382844006976928398010846062018500893155019165263553434 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod_end | 72537246074041500947350486861688586416151994190557107167878685800036857489259 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_rma | 2800082037284827057380579878701131987086708448118096867856959655209587422600 | None |
---- STDERR ----
Another command (pid=411960) is running. Waiting for it to complete on the server (server_pid=264734)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_volatile_raw_unlock | 14752263055175744907242613474013408046008581102134494923144005515292463306689 | None |
Another command (pid=327396) is running. Waiting for it to complete on the server (server_pid=264734)...
Another command (pid=310796) is running. Waiting for it to complete on the server (server_pid=264734)...
Another command (pid=323981) is running. Waiting for it to complete on the server (server_pid=264734)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_raw_unlock | 92637370744136710822711202617324109780526313363295365100784986140649423004838 | None |
Another command (pid=270577) is running. Waiting for it to complete on the server (server_pid=264734)...
Another command (pid=282356) is running. Waiting for it to complete on the server (server_pid=264734)...
Another command (pid=307783) is running. Waiting for it to complete on the server (server_pid=264734)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_self_hash | 16976275309446434401582874108850299578548343916431584960592590836471712582805 | None |
Another command (pid=272795) is running. Waiting for it to complete on the server (server_pid=264734)...
Another command (pid=272363) is running. Waiting for it to complete on the server (server_pid=264734)...
Another command (pid=293698) is running. Waiting for it to complete on the server (server_pid=264734)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). | 30 test runs | |||
| chip_tl_errors | 16310393994988690468003259507477191308165210230315320059372485811159277901666 | 217 |
TL item was: req: (cip_tl_seq_item@31456) { a_addr: 'h105a4 a_data: 'hb884a056 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hc a_opcode: 'h4 a_user: 'h1b65d d_param: 'h0 d_source: 'hc d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1987.467728 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 6767427630821267764518941990178026807221358206476331159738604437777532036103 | 217 |
TL item was: req: (cip_tl_seq_item@34084) { a_addr: 'h105bc a_data: 'hff764673 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h12 a_opcode: 'h4 a_user: 'h18614 d_param: 'h0 d_source: 'h12 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2132.787833 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 63489071977741251749842502622331758290315637857018453911733091419572286555544 | 224 |
TL item was: req: (cip_tl_seq_item@31516) { a_addr: 'h10370 a_data: 'hffb1bc08 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h17 a_opcode: 'h4 a_user: 'h19e02 d_param: 'h0 d_source: 'h17 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2502.040645 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 32463588574085390948626979825231557661332045642497999774644057237709369630729 | 217 |
TL item was: req: (cip_tl_seq_item@38718) { a_addr: 'h105e0 a_data: 'h39b9e872 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h23 a_opcode: 'h4 a_user: 'h19265 d_param: 'h0 d_source: 'h23 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2611.754582 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 31708399428421437264470493027571451425944726962991403816017689484675707854090 | 224 |
TL item was: req: (cip_tl_seq_item@31688) { a_addr: 'h1040c a_data: 'h88070bb3 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3e a_opcode: 'h4 a_user: 'h18dd6 d_param: 'h0 d_source: 'h3e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2063.178520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 58579120933541082361332509717717425450735441945514132720727791120927497514007 | 218 |
TL item was: req: (cip_tl_seq_item@192894) { a_addr: 'h106ac a_data: 'h7c536278 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h29 a_opcode: 'h4 a_user: 'h1aecf d_param: 'h0 d_source: 'h29 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3114.368080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 14178655663723786955098113403273124056159634273734068715264351438551211190110 | 222 |
TL item was: req: (cip_tl_seq_item@34026) { a_addr: 'h10704 a_data: 'ha39e9295 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h31 a_opcode: 'h4 a_user: 'h19552 d_param: 'h0 d_source: 'h31 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2248.928808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 57424181098320500488154399149700009600059606930375775095168360499550287570160 | 223 |
TL item was: req: (cip_tl_seq_item@94722) { a_addr: 'h10448 a_data: 'hbe1a86d0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h27 a_opcode: 'h4 a_user: 'h1a9a8 d_param: 'h0 d_source: 'h27 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3260.006725 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 49210897344730316462192678451644662181825767639039042206672413566873718390462 | 217 |
TL item was: req: (cip_tl_seq_item@33014) { a_addr: 'h10710 a_data: 'h77ac888a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h34 a_opcode: 'h4 a_user: 'h1bd5a d_param: 'h0 d_source: 'h34 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1799.622212 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 26727501857656055656908018001265046253783055428236290600532112605934292985064 | 222 |
TL item was: req: (cip_tl_seq_item@33434) { a_addr: 'h106d4 a_data: 'h9f1e8884 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h7 a_opcode: 'h4 a_user: 'h1aea5 d_param: 'h0 d_source: 'h7 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2765.257796 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 51413825869382223540881736635117406443503673605732927798433550683089926131232 | 217 |
TL item was: req: (cip_tl_seq_item@31556) { a_addr: 'h1043c a_data: 'h226e95cd a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h15 a_opcode: 'h4 a_user: 'h1b196 d_param: 'h0 d_source: 'h15 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2488.760062 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 76637365325781003701192512480574723547375917470540036501900958506864559762289 | 217 |
TL item was: req: (cip_tl_seq_item@33854) { a_addr: 'h107dc a_data: 'h858d1a05 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h13 a_opcode: 'h4 a_user: 'h1bd46 d_param: 'h0 d_source: 'h13 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2497.742514 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 50432128139341546883294615993464043668287892896226332018527919299734803336903 | 217 |
TL item was: req: (cip_tl_seq_item@37556) { a_addr: 'h10384 a_data: 'h4cbf32f5 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hc a_opcode: 'h4 a_user: 'h1b6da d_param: 'h0 d_source: 'hc d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2244.736994 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 19750443390770675514265694873028499682719465896575950605390885389328595030169 | 217 |
TL item was: req: (cip_tl_seq_item@41550) { a_addr: 'h107ac a_data: 'h487aff6e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3 a_opcode: 'h4 a_user: 'h1a9c3 d_param: 'h0 d_source: 'h3 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1839.490000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 63745860596306515117507857354617976663429609519288396569517959273023556835299 | 217 |
TL item was: req: (cip_tl_seq_item@32064) { a_addr: 'h10444 a_data: 'h57ccaf86 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h13 a_opcode: 'h4 a_user: 'h1b1dd d_param: 'h0 d_source: 'h13 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2484.222775 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 7169364012275549095009313103659037854307751395125754747510098936586871310929 | 217 |
TL item was: req: (cip_tl_seq_item@32798) { a_addr: 'h10518 a_data: 'h17bacfb2 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3f a_opcode: 'h4 a_user: 'h1a2ea d_param: 'h0 d_source: 'h3f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2221.544250 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 111874741212827796931435903202590945976601465767278820387807139498722422254078 | 217 |
TL item was: req: (cip_tl_seq_item@31968) { a_addr: 'h10368 a_data: 'h3822b79b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h31 a_opcode: 'h4 a_user: 'h1ae52 d_param: 'h0 d_source: 'h31 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2275.539422 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 47822858500114774219443822963415142855373007503853432363733208049491130685738 | 217 |
TL item was: req: (cip_tl_seq_item@32136) { a_addr: 'h106d0 a_data: 'hbc01f657 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h9 a_opcode: 'h4 a_user: 'h1a224 d_param: 'h0 d_source: 'h9 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2242.404946 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 4444995197261739184944136300543103990868708587198576869099341124953955454636 | 217 |
TL item was: req: (cip_tl_seq_item@35556) { a_addr: 'h105d0 a_data: 'h1ce2a928 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h32 a_opcode: 'h4 a_user: 'h1ae39 d_param: 'h0 d_source: 'h32 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2154.156077 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 6246341824052561357307118548260176168865158567871337869690654341378318841 | 217 |
TL item was: req: (cip_tl_seq_item@33420) { a_addr: 'h10620 a_data: 'hfc18b9fb a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1e a_opcode: 'h4 a_user: 'h18613 d_param: 'h0 d_source: 'h1e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2411.113408 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 12043347308360464489900602040639327522935746713561870404743549419586363270396 | 217 |
TL item was: req: (cip_tl_seq_item@36846) { a_addr: 'h10364 a_data: 'ha5abf3b5 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h10 a_opcode: 'h4 a_user: 'h1b61a d_param: 'h0 d_source: 'h10 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2740.981458 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 81829135718627574396672094347695422765215234245140054609934514107033090830378 | 217 |
TL item was: req: (cip_tl_seq_item@33356) { a_addr: 'h106b0 a_data: 'he579cffb a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h9 a_opcode: 'h4 a_user: 'h1920c d_param: 'h0 d_source: 'h9 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1730.367529 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 27524763760595915020018572065893910797676423834479979485012854011702939491831 | 217 |
TL item was: req: (cip_tl_seq_item@35994) { a_addr: 'h104b8 a_data: 'h39e20199 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h25 a_opcode: 'h4 a_user: 'h18dfe d_param: 'h0 d_source: 'h25 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2062.136154 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 11601980505716067947506694461672014615862018862460643808053018718301315823742 | 217 |
TL item was: req: (cip_tl_seq_item@31720) { a_addr: 'h107a8 a_data: 'h36ddb24f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h24 a_opcode: 'h4 a_user: 'h1a50f d_param: 'h0 d_source: 'h24 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2522.919703 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 61478237511331893846405714239830993835518610279398722523742014985332386985178 | 217 |
TL item was: req: (cip_tl_seq_item@44168) { a_addr: 'h107d0 a_data: 'h865ea9e4 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hf a_opcode: 'h4 a_user: 'h1a51a d_param: 'h0 d_source: 'hf d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2177.325652 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 16589709450074453504198696864200433753468877540542781488045087902221192151321 | 217 |
TL item was: req: (cip_tl_seq_item@35406) { a_addr: 'h10790 a_data: 'h9630b53 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h14 a_opcode: 'h4 a_user: 'h18d80 d_param: 'h0 d_source: 'h14 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1866.812925 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 85156431107692271135765859612533034200821118480638489250182478713022895644411 | 217 |
TL item was: req: (cip_tl_seq_item@32294) { a_addr: 'h10414 a_data: 'hbec60ea6 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hf a_opcode: 'h4 a_user: 'h1bdb5 d_param: 'h0 d_source: 'hf d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1825.837475 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 23280342609519261306719592660915133460248383414986037249954876956394455912671 | 217 |
TL item was: req: (cip_tl_seq_item@31456) { a_addr: 'h107c0 a_data: 'h3e6d0c91 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h13 a_opcode: 'h4 a_user: 'h181f1 d_param: 'h0 d_source: 'h13 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2722.222162 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 104816954937012339687343042953464712254065646119221844369109793008773517963137 | 217 |
TL item was: req: (cip_tl_seq_item@34090) { a_addr: 'h105a4 a_data: 'h31908408 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h36 a_opcode: 'h4 a_user: 'h1b66b d_param: 'h0 d_source: 'h36 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2817.636312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 97797827689426718416350957743425270234847247508866352084029686715822726799053 | 217 |
TL item was: req: (cip_tl_seq_item@40914) { a_addr: 'h106fc a_data: 'h837d2683 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h5 a_opcode: 'h4 a_user: 'h1a2a1 d_param: 'h0 d_source: 'h5 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1980.052500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | 13 test runs | |||
| chip_sw_rv_timer_systick_test | 17160797756063957918248610784656000965784366389624010556036072841926443466923 | None | ||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 77724915855322115771321264145492783852726873664733322534076621348352867841346 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 16004276182841476914993640049725865940096270338398335897958598705087136923753 | None | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 100989207431197913581738992472801413430644757653950754676632396304002812428892 | None | ||
| ate_bootstrap_disjoint | 9935743984905447680639615493612450257628672950466434447302885370091049331039 | None | ||
| chip_sw_rv_timer_systick_test | 100616923996969888541075408953484246325700291348547715960795084686080132126527 | None | ||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 58536041757908791102812881278988974451903677017701547295389044039492781343675 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 6103858436761258473585178163415276094111400222196918913838077138489432655904 | None | ||
| ate_bootstrap_disjoint | 39041899821511727928945984034076647569496588719203433837899377115231461317200 | None | ||
| chip_sw_rv_timer_systick_test | 101387954051913124467668142836767623866827720939265877405733296337172362800523 | None | ||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 38982610769440155510306008953668934211964154811592115516399905528556043970888 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 106202389267359548444514082050246658735053755746432215792218562400294001493355 | None | ||
| ate_bootstrap_disjoint | 115667826039441171834363416737640243835701712011729132425836894187736978719676 | None | ||
| Offending '(rstreqs[*] && (reset_cause == HwReq))' | 10 test runs | |||
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 712264055272610647221783714961738794066894169715207953728385563444271958504 | 344 |
UVM_ERROR @ 13281.063500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 13281.063500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 28956520360870952956334149262873705161905045631083794799496983120501004866853 | 327 |
UVM_ERROR @ 10488.822000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 10488.822000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_deep_sleep_por_reset | 6292054823104778807141198657969605074104341884906093794999517980331790821548 | 325 |
UVM_ERROR @ 7008.172500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7008.172500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 28936685950130375321150042324883634442281973191363322346512761935581957610516 | 344 |
UVM_ERROR @ 14011.497500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 14011.497500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_deep_sleep_por_reset | 7823771303244964878499104779137275684411349419698120679837235573107696817347 | 325 |
UVM_ERROR @ 7341.436000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7341.436000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_aon_timer_wdog_bite_reset | 66721919137119230111080222898044520226807297514291071953493508571967129364510 | 319 |
UVM_ERROR @ 8354.610000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8354.610000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 63317491811671514481907530629518551986575582422169995739598092024570403617352 | 315 |
UVM_ERROR @ 5277.889000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5277.889000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 24211793356862286935217201752755967432052776513672942734945564442326445726391 | 327 |
UVM_ERROR @ 9100.453000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9100.453000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_deep_sleep_por_reset | 41846683027483465270555293658406196665771783639484986293552899042470583712958 | 325 |
UVM_ERROR @ 7687.642000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7687.642000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_aon_timer_wdog_bite_reset | 19740402324473576960806933388930318316356354387105343867168611954148262265903 | 319 |
UVM_ERROR @ 7417.426000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7417.426000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' | 9 test runs | |||
| chip_sw_otp_ctrl_escalation | 57801914912907588821660715204374698559370497873614310358681586548703440078220 | 316 |
UVM_ERROR @ 3132.629580 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3132.629580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_csrng_fuse_en_sw_app_read_test | 109524311772542416318635352153158181235653447232635193188877167564386181028686 | 312 |
UVM_ERROR @ 3217.571272 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3217.571272 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_csrng_fuse_en_sw_app_read_test | 81380369395178475375948264856226846888322568639076029883120594884606028676072 | 312 |
UVM_ERROR @ 2638.857910 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2638.857910 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 30409761577182022057498183898569861197932864449853494476124108413530274350626 | 317 |
UVM_ERROR @ 2716.278048 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2716.278048 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 29239039329764006410680773285539356740546354584612205675228748358696300796443 | 317 |
UVM_ERROR @ 2848.250952 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2848.250952 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 472379935962215538846851136027618191786852525229511889408800829818541951642 | 317 |
UVM_ERROR @ 2914.095324 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2914.095324 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 18086942583633581137117390748275111437362609423570368775725751141419112923846 | 317 |
UVM_ERROR @ 2741.804412 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2741.804412 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 79716135166940431384726851623826231801788311675753667763535921173367305050172 | 322 |
UVM_ERROR @ 3151.978988 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3151.978988 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 33779418905044824446987111042597892726743193003286122419038676172907549967261 | 317 |
UVM_ERROR @ 3511.567040 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3511.567040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected | 9 test runs | |||
| chip_sw_lc_walkthrough_dev | 40601448571644389329636050509170548515541303439599783856640500691242389476915 | 369 |
UVM_INFO @ 9245.355688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_prod | 71525620337085010129403143678246970040664879007430486853267785700515178209417 | 369 |
UVM_INFO @ 11784.032472 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_rma | 62810762340223437846250456336867224854990046450746263226456947345024749141676 | 341 |
UVM_INFO @ 7643.110568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_dev | 33208219808590088796855863738031703004092166090418512667687382933091949468789 | 369 |
UVM_INFO @ 8992.959775 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_prod | 44534628897111181842387951908437495508535474844743688821861591976652301232586 | 369 |
UVM_INFO @ 9413.029925 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_rma | 82331121545661822172670696737032436620516959515960139662466857449128250121577 | 341 |
UVM_INFO @ 6176.894662 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_dev | 16236216931288021046785260223961293372235147373375102584573360547344080437931 | 369 |
UVM_INFO @ 8780.453884 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_prod | 63462951722135301687370851944329480391679366950224639361420538475096057377088 | 369 |
UVM_INFO @ 10052.219036 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_rma | 74269146047232730479479530545705433359547642330116902535994412429403131986984 | 341 |
UVM_INFO @ 7129.198655 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' | 6 test runs | |||
| chip_sw_pwrmgr_sleep_power_glitch_reset | 102651093443452214042546182714187827406417616840800010480037142774036808269122 | 313 |
UVM_ERROR @ 3294.700968 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3294.700968 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 49826875360388053797777255713496462427022375808941134210696976339637835398983 | 329 |
UVM_ERROR @ 6766.480800 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 6766.480800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_sleep_power_glitch_reset | 105333830056478282468867938522847870160248847779224795257802209788440457306248 | 313 |
UVM_ERROR @ 2607.783053 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2607.783053 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 40337926130152032295654928035604697799179520978619251649926077768617574330219 | 380 |
UVM_ERROR @ 16447.492059 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 16447.492059 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_sleep_power_glitch_reset | 19348693240427832458474643885717647536862851399356675623050945861038052765216 | 313 |
UVM_ERROR @ 2955.756375 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2955.756375 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 37852522304280234362273701878143117738547706645029910804270767056067299710148 | 367 |
UVM_ERROR @ 18158.416982 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 18158.416982 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '((~rst_ni) === (~seed_en_q))' | 4 test runs | |||
| chip_sw_pwrmgr_full_aon_reset | 91698402344730899439504473454799827413285399915705737275470619312253520033680 | 320 |
UVM_ERROR @ 6504.870704 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 6504.870704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 93831993146064578749503647571368132012380792043643016596090774136119488010489 | 230 |
UVM_ERROR @ 4256.705000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 4256.705000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_full_aon_reset | 13112145390721126853906812777963234443265446044630001789032631751022356239843 | 303 |
UVM_ERROR @ 2921.155853 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 2921.155853 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_full_aon_reset | 87138892532378681786339818801896403093270432268999516356568936463031006362650 | 316 |
UVM_ERROR @ 6584.628992 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 6584.628992 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Error-[NOA] Null object access | 4 test runs | |||
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 85094698488767226563235986970977445589042514970712089254502684383013103482311 | 327 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| rom_e2e_jtag_debug_dev | 91221999381544225257010854248354705975961542949219950825535318276822214209588 | 319 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 71402255776312892405329177451387275209979085050921572751760011590475483569830 | 327 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 37787006725151486226824322199200085902846049031875093934134351981786334372864 | 327 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| UVM_ERROR @ * us: (cip_base_vseq.sv:912) virtual_sequencer [chip_sw_all_escalation_resets_vseq] Alert usbdev_fatal_fault fired unexpectedly. | 4 test runs | |||
| chip_sw_all_escalation_resets | 57739784261681001166159348458136824830434994678197113609369740323149026782339 | 321 |
UVM_INFO @ 2972.616906 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 110873158499068557164705453565759433408530414831840433023250292639048821610580 | 316 |
UVM_INFO @ 2731.494040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 97161211543898082719305134543689152052630017562486121151218134277880728119448 | 321 |
UVM_INFO @ 2849.340816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 94409096418771745732563437422331274407545549307511286343123321059614097924759 | 321 |
UVM_INFO @ 3741.930452 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty | 3 test runs | |||
| chip_sw_spi_device_pass_through_collision | 6916007874932327146643427545480062128418964878536152626628786810269933333665 | 320 |
UVM_INFO @ 3034.260220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_spi_device_pass_through_collision | 65638020374432354671937601560712231003002251098244273514104728895918600795805 | 320 |
UVM_INFO @ 3217.405707 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_spi_device_pass_through_collision | 76317413286314679843176600448422359030339337935961932861955448550031512785330 | 320 |
UVM_INFO @ 3365.207119 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected | 3 test runs | |||
| chip_sw_flash_ctrl_lc_rw_en | 47937970017889027155574642749406314608857919479231722845775621839062271461771 | 309 |
UVM_INFO @ 3289.473636 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_flash_ctrl_lc_rw_en | 114952292799293439135857294989282574622353451920357340478703125075762844328687 | 309 |
UVM_INFO @ 3070.560380 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_flash_ctrl_lc_rw_en | 2957877770329825346068002501608643965714089593866708513297712001637939345111 | 309 |
UVM_INFO @ 2594.815864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * | 3 test runs | |||
| chip_sw_otp_ctrl_lc_signals_rma | 115302441391960096512619601086840959245704540484466619185590160937369335138589 | 342 |
UVM_INFO @ 6926.368734 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_otp_ctrl_lc_signals_rma | 40600235020375477077142677558156859422842354793659653212124667246801458120982 | 342 |
UVM_INFO @ 7655.575159 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_otp_ctrl_lc_signals_rma | 90348735539182694532427502299596910398867307826339157129846888706461167022178 | 342 |
UVM_INFO @ 7348.580266 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected | 3 test runs | |||
| chip_sw_clkmgr_jitter_frequency | 39964362455229974177339904238848441630764129870395408466411918822770773243480 | 343 |
UVM_INFO @ 3361.909659 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_clkmgr_jitter_frequency | 72536354479991780340146545081119534502197837814935375330128421098209947992758 | 343 |
UVM_INFO @ 3251.602206 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_clkmgr_jitter_frequency | 68937052949959854560379136876973504551252625938806205206991785625530096560848 | 343 |
UVM_INFO @ 3901.659210 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch | 3 test runs | |||
| chip_rv_dm_lc_disabled | 9568703498477683150808116559461782983611803547419942168623389427274533671846 | 235 |
UVM_INFO @ 5483.691609 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_rv_dm_lc_disabled | 51499707672022069839314406853093510277885413345611426146033511964421758329952 | 225 |
UVM_INFO @ 4169.007348 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_rv_dm_lc_disabled | 19880708378407417465844940235419125197911871945549190953713281396781128686577 | 236 |
UVM_INFO @ 5279.171040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * | 3 test runs | |||
| chip_sw_power_idle_load | 65950786331304228499471889776481839419457095805961363346835103389909355500246 | 312 |
UVM_INFO @ 3616.411000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_power_idle_load | 19628231410697902712491367026121464204569376678972667098957984073618251535915 | 312 |
UVM_INFO @ 2978.795000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_power_idle_load | 52537227927588874369250009529195742340256431164098168692696366987114208633868 | 312 |
UVM_INFO @ 3409.395000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * | 3 test runs | |||
| chip_sw_power_sleep_load | 2126243898115194783530637251170058907084843317467872376341665889281086028 | 319 |
UVM_INFO @ 3375.912000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_power_sleep_load | 39100792765251240536138658678967845795518496682557150538751471365944225377291 | 318 |
UVM_INFO @ 3521.717000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_power_sleep_load | 5789739485064185471034546018765128924328665495965077180104155451427920309083 | 318 |
UVM_INFO @ 3576.870000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * | 3 test runs | |||
| chip_sw_ast_clk_rst_inputs | 20242249615054159556603765477439473115208987657682640358754482505193569763312 | 327 |
UVM_INFO @ 11734.736636 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_ast_clk_rst_inputs | 49359680872014447099083115173722270890721730989268342008271145959000804965385 | 327 |
UVM_INFO @ 10033.849285 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_ast_clk_rst_inputs | 5566169083191990364024608408960169117029581292088733757942365384806847552458 | 327 |
UVM_INFO @ 13507.709327 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) | 3 test runs | |||
| ate_bootstrap_flash_erase | 16193490153248483663173200595531001691120811066357946199484447897641178281166 | 272 |
UVM_INFO @ 10010.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| ate_bootstrap_flash_erase | 69439725076184699103824995858190929033147728507896681900944951026342186002911 | 272 |
UVM_INFO @ 10010.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| ate_bootstrap_flash_erase | 46757814971136312716073300884592334217214476727453128102306324850054542548933 | 272 |
UVM_INFO @ 10010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '$stable(key_data_i)' | 3 test runs | |||
| rom_keymgr_functest | 109011948260975135803958027642692101792431117586907466206961693522312038454008 | 327 |
UVM_ERROR @ 5055.687992 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5055.687992 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_keymgr_functest | 34651396661123833552225386053789745829708893865938194260804915047320063950705 | 327 |
UVM_ERROR @ 3818.949580 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 3818.949580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_keymgr_functest | 85090896432089311102267316491620157102954895388353884121029923996806555921770 | 327 |
UVM_ERROR @ 5140.981516 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5140.981516 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got * | 3 test runs | |||
| chip_sw_all_escalation_resets | 60548001256610109402352899582232133462553029314166051418303337533167515650902 | 317 |
UVM_INFO @ 2705.565495 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 34141095195338908916732907261466200091966650155308962256139409643127265255954 | 322 |
UVM_INFO @ 3310.321454 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 35727729650625846091817958511457141631257006810748214353020359261216442507563 | 317 |
UVM_INFO @ 2986.001523 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! | 2 test runs | |||
| chip_sw_alert_test | 4776597864413770603767705032232215432255126842075576045405819305643755339255 | 307 |
UVM_INFO @ 3021.198520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_test | 32504210702411879299605239141651058883734871732471597475792132126852140959465 | 307 |
UVM_INFO @ 2693.669704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * | 2 test runs | |||
| rom_e2e_keymgr_init_rom_ext_no_meas | 77689855863466981840535016555508591710689154741500025985245929631124476254898 | 319 |
UVM_INFO @ 16223.662651 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_keymgr_init_rom_ext_no_meas | 42510581606371853747675075115475785288330546363569299009890749844181932737485 | 319 |
UVM_INFO @ 15935.613159 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '(!$isunknown(pin_wkup_req_o))' | 1 test run | |||
| chip_sw_sleep_pin_wake | 77905894180052107980065354591961531129823981196642221831296425564575697055725 | 318 |
UVM_ERROR @ 2604.277500 us: (pinmux.sv:662) [ASSERT FAILED] AonWkupReqKnownO_A
UVM_INFO @ 2604.277500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode | 1 test run | |||
| chip_sw_otp_ctrl_rot_auth_config | 58050190564825787865529011422998549849799267155352488416107799275330300137153 | 282 |
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched! | 1 test run | |||
| chip_sw_lc_ctrl_rand_to_scrap | 77547955004812060251308048762204990405822645646281224682411292564031802664377 | 313 |
UVM_INFO @ 26717.951511 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_testunlocks_vseq] max attempt reached to get lc status LcExtClockSwitched! | 1 test run | |||
| chip_sw_lc_walkthrough_testunlocks | 89300979520902193639708874443057160124677303674035815967968219042612740500153 | 304 |
UVM_INFO @ 26178.431097 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds | 1 test run | |||
| rom_e2e_jtag_debug_test_unlocked0 | 99805937912832585794014478807324513780787539095850957539215000867298878707067 | 318 |
UVM_INFO @ 4337.767713 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (jtag_rv_debugger.sv:613) [debugger] Check failed dcsr.cause == exp_debug_cause (* [*] vs * [*]) | 1 test run | |||
| rom_e2e_jtag_debug_rma | 23034514429600466364264018214703459891366329242374467566474271033667152207248 | 317 |
UVM_INFO @ 4172.360370 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert *! | 1 test run | |||
| chip_sw_alert_test | 63295171402325898061001974665810627054528001083094035857367710098905332422737 | 307 |
UVM_INFO @ 3791.276324 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] | 1 test run | |||
| chip_sw_sleep_pin_mio_dio_val | 103874128442502953162503351368580999748605248644871044533645517451643647398313 | 451 |
UVM_INFO @ 2902.765000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|