Simulation Results

Simulation Results: otbn

24/05/2026 04:19:36 DVSim: v1.49.0 sha: 32edacb json Branch: reseed_opt Tool: xcelium [unknown]

Coverage statistics

Total
98.07 %

code
96.85 %

assert
97.37 %

func
100.00 %

block
99.54 %

line
99.64 %

branch
94.13 %

toggle
93.62 %

FSM
100.00 %

Validation stages

V1		99.14%
V2		98.16%
V2S		97.26%
V3		30.00%
unmapped		100.00%

115/116 passed

99.14 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	otbn_smoke	38.000s	260.036us	1	1	100.00
single_binary				99	100	99.00
	otbn_single	126.000s	519.087us	99	100	99.00
csr_hw_reset				1	1	100.00
	otbn_csr_hw_reset	37.000s	25.465us	1	1	100.00
csr_rw				5	5	100.00
	otbn_csr_rw	39.000s	25.165us	5	5	100.00
csr_bit_bash				1	1	100.00
	otbn_csr_bit_bash	39.000s	181.803us	1	1	100.00
csr_aliasing				1	1	100.00
	otbn_csr_aliasing	37.000s	22.504us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	otbn_csr_mem_rw_with_rand_reset	39.000s	42.207us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	otbn_csr_rw	39.000s	25.165us	5	5	100.00
	otbn_csr_aliasing	37.000s	22.504us	1	1	100.00
mem_walk				1	1	100.00
	otbn_mem_walk	187.000s	27228.696us	1	1	100.00
mem_partial_access				1	1	100.00
	otbn_mem_partial_access	57.000s	1141.646us	1	1	100.00

160/163 passed

98.16 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
reset_recovery				10	10	100.00
	otbn_reset	88.000s	1233.927us	10	10	100.00
multi_error				1	1	100.00
	otbn_multi_err	87.000s	603.455us	1	1	100.00
back_to_back				9	10	90.00
	otbn_multi	91.000s	135.669us	9	10	90.00
stress_all				10	10	100.00
	otbn_stress_all	114.000s	913.482us	10	10	100.00
lc_escalation				58	60	96.67
	otbn_escalate	57.000s	159.905us	58	60	96.67
zero_state_err_urnd				5	5	100.00
	otbn_zero_state_err_urnd	32.000s	25.783us	5	5	100.00
sw_errs_fatal_chk				10	10	100.00
	otbn_sw_errs_fatal_chk	45.000s	163.380us	10	10	100.00
alert_test				10	10	100.00
	otbn_alert_test	37.000s	21.999us	10	10	100.00
intr_test				10	10	100.00
	otbn_intr_test	37.000s	49.649us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	otbn_tl_errors	32.000s	197.585us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	otbn_tl_errors	32.000s	197.585us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	otbn_csr_hw_reset	37.000s	25.465us	1	1	100.00
	otbn_csr_rw	39.000s	25.165us	5	5	100.00
	otbn_csr_aliasing	37.000s	22.504us	1	1	100.00
	otbn_same_csr_outstanding	37.000s	56.097us	5	5	100.00
tl_d_partial_access				12	12	100.00
	otbn_csr_hw_reset	37.000s	25.465us	1	1	100.00
	otbn_csr_rw	39.000s	25.165us	5	5	100.00
	otbn_csr_aliasing	37.000s	22.504us	1	1	100.00
	otbn_same_csr_outstanding	37.000s	56.097us	5	5	100.00

V2S

320/329 passed

97.26 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
mem_integrity				25	25	100.00
	otbn_imem_err	37.000s	72.193us	10	10	100.00
	otbn_dmem_err	43.000s	34.837us	15	15	100.00
internal_integrity				16	17	94.12
	otbn_alu_bignum_mod_err	43.000s	159.554us	5	5	100.00
	otbn_controller_ispr_rdata_err	37.000s	12.842us	4	5	80.00
	otbn_mac_bignum_acc_err	33.000s	199.234us	5	5	100.00
	otbn_urnd_err	30.000s	10.463us	2	2	100.00
illegal_bus_access				4	5	80.00
	otbn_illegal_mem_acc	38.000s	27.510us	4	5	80.00
otbn_mem_gnt_acc_err				2	2	100.00
	otbn_mem_gnt_acc_err	33.000s	38.007us	2	2	100.00
otbn_non_sec_partial_wipe				9	10	90.00
	otbn_partial_wipe	31.000s	12.519us	9	10	90.00
tl_intg_err				30	30	100.00
	otbn_sec_cm	321.000s	1572.939us	5	5	100.00
	otbn_tl_intg_err	38.000s	74.425us	25	25	100.00
passthru_mem_tl_intg_err				4	5	80.00
	otbn_passthru_mem_tl_intg_err	59.000s	225.859us	4	5	80.00
prim_fsm_check				5	5	100.00
	otbn_sec_cm	321.000s	1572.939us	5	5	100.00
prim_count_check				5	5	100.00
	otbn_sec_cm	321.000s	1572.939us	5	5	100.00
sec_cm_mem_scramble				1	1	100.00
	otbn_smoke	38.000s	260.036us	1	1	100.00
sec_cm_data_mem_integrity				15	15	100.00
	otbn_dmem_err	43.000s	34.837us	15	15	100.00
sec_cm_instruction_mem_integrity				10	10	100.00
	otbn_imem_err	37.000s	72.193us	10	10	100.00
sec_cm_bus_integrity				25	25	100.00
	otbn_tl_intg_err	38.000s	74.425us	25	25	100.00
sec_cm_controller_fsm_global_esc				58	60	96.67
	otbn_escalate	57.000s	159.905us	58	60	96.67
sec_cm_controller_fsm_local_esc				39	40	97.50
	otbn_imem_err	37.000s	72.193us	10	10	100.00
	otbn_dmem_err	43.000s	34.837us	15	15	100.00
	otbn_zero_state_err_urnd	32.000s	25.783us	5	5	100.00
	otbn_illegal_mem_acc	38.000s	27.510us	4	5	80.00
	otbn_sec_cm	321.000s	1572.939us	5	5	100.00
sec_cm_controller_fsm_sparse				5	5	100.00
	otbn_sec_cm	321.000s	1572.939us	5	5	100.00
sec_cm_scramble_key_sideload				99	100	99.00
	otbn_single	126.000s	519.087us	99	100	99.00
sec_cm_scramble_ctrl_fsm_local_esc				39	40	97.50
	otbn_imem_err	37.000s	72.193us	10	10	100.00
	otbn_dmem_err	43.000s	34.837us	15	15	100.00
	otbn_zero_state_err_urnd	32.000s	25.783us	5	5	100.00
	otbn_illegal_mem_acc	38.000s	27.510us	4	5	80.00
	otbn_sec_cm	321.000s	1572.939us	5	5	100.00
sec_cm_scramble_ctrl_fsm_sparse				5	5	100.00
	otbn_sec_cm	321.000s	1572.939us	5	5	100.00
sec_cm_start_stop_ctrl_fsm_global_esc				58	60	96.67
	otbn_escalate	57.000s	159.905us	58	60	96.67
sec_cm_start_stop_ctrl_fsm_local_esc				39	40	97.50
	otbn_imem_err	37.000s	72.193us	10	10	100.00
	otbn_dmem_err	43.000s	34.837us	15	15	100.00
	otbn_zero_state_err_urnd	32.000s	25.783us	5	5	100.00
	otbn_illegal_mem_acc	38.000s	27.510us	4	5	80.00
	otbn_sec_cm	321.000s	1572.939us	5	5	100.00
sec_cm_start_stop_ctrl_fsm_sparse				5	5	100.00
	otbn_sec_cm	321.000s	1572.939us	5	5	100.00
sec_cm_data_reg_sw_sca				99	100	99.00
	otbn_single	126.000s	519.087us	99	100	99.00
sec_cm_ctrl_redun				12	12	100.00
	otbn_ctrl_redun	35.000s	53.378us	12	12	100.00
sec_cm_pc_ctrl_flow_redun				5	5	100.00
	otbn_pc_ctrl_flow_redun	38.000s	18.500us	5	5	100.00
sec_cm_rnd_bus_consistency				5	5	100.00
	otbn_rnd_sec_cm	102.000s	569.195us	5	5	100.00
sec_cm_rnd_rng_digest				5	5	100.00
	otbn_rnd_sec_cm	102.000s	569.195us	5	5	100.00
sec_cm_rf_base_data_reg_sw_integrity				10	10	100.00
	otbn_rf_base_intg_err	38.000s	49.503us	10	10	100.00
sec_cm_rf_base_data_reg_sw_glitch_detect				5	5	100.00
	otbn_sec_cm	321.000s	1572.939us	5	5	100.00
sec_cm_stack_wr_ptr_ctr_redun				5	5	100.00
	otbn_sec_cm	321.000s	1572.939us	5	5	100.00
sec_cm_rf_bignum_data_reg_sw_integrity				9	10	90.00
	otbn_rf_bignum_intg_err	38.000s	55.699us	9	10	90.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect				5	5	100.00
	otbn_sec_cm	321.000s	1572.939us	5	5	100.00
sec_cm_loop_stack_ctr_redun				5	5	100.00
	otbn_sec_cm	321.000s	1572.939us	5	5	100.00
sec_cm_loop_stack_addr_integrity				5	5	100.00
	otbn_stack_addr_integ_chk	36.000s	21.643us	5	5	100.00
sec_cm_call_stack_addr_integrity				5	5	100.00
	otbn_stack_addr_integ_chk	36.000s	21.643us	5	5	100.00
sec_cm_start_stop_ctrl_state_consistency				7	7	100.00
	otbn_sec_wipe_err	35.000s	67.442us	7	7	100.00
sec_cm_data_mem_sec_wipe				99	100	99.00
	otbn_single	126.000s	519.087us	99	100	99.00
sec_cm_instruction_mem_sec_wipe				99	100	99.00
	otbn_single	126.000s	519.087us	99	100	99.00
sec_cm_data_reg_sw_sec_wipe				99	100	99.00
	otbn_single	126.000s	519.087us	99	100	99.00
sec_cm_write_mem_integrity				9	10	90.00
	otbn_multi	91.000s	135.669us	9	10	90.00
sec_cm_ctrl_flow_count				99	100	99.00
	otbn_single	126.000s	519.087us	99	100	99.00
sec_cm_ctrl_flow_sca				99	100	99.00
	otbn_single	126.000s	519.087us	99	100	99.00
sec_cm_data_mem_sw_noaccess				5	5	100.00
	otbn_sw_no_acc	33.000s	26.072us	5	5	100.00
sec_cm_key_sideload				99	100	99.00
	otbn_single	126.000s	519.087us	99	100	99.00
sec_cm_tlul_fifo_ctr_redun				5	5	100.00
	otbn_sec_cm	321.000s	1572.939us	5	5	100.00

3/10 passed

30.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				3	10	30.00
	otbn_stress_all_with_rand_reset	370.000s	4229.865us	3	10	30.00

unmapped

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	1	100.00
	otbn_smoke_vectorized	37.000s	90.977us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.				4 test runs
	otbn_stress_all_with_rand_reset	99684609558862722576774324166157169368724685691493552087586543683342332464753	154	UVM_INFO @ 91063215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_passthru_mem_tl_intg_err	73825342210106168618280888022159844772138085536388625422727051057200005009461	121	UVM_INFO @ 223537353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_multi	10338352103538185375247741210376345765628832347046560534545386280478956800188	148	UVM_INFO @ 35039773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_single	53789790020501793613825729036280393606467005096484032080760491087916609253612	108	UVM_INFO @ 90679559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error				4 test runs
	otbn_controller_ispr_rdata_err	56226825898183028387809076280684898777726962888342071819907574167126539426931	112	UVM_INFO @ 59584138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_rf_bignum_intg_err	25474847596467085308538658146703589467451700343331688609138734398637641724362	109	UVM_INFO @ 62624357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	53031956325957220910017960854907966044606438013646129540972166383513683144425	148	UVM_INFO @ 115190493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_escalate	53621953699059606843377320176763540360845448212256754182204425022596159929861	106	UVM_INFO @ 30058204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				3 test runs
	otbn_stress_all_with_rand_reset	18602272497836013802354209787840982141137759985290541131005138280805926730407	297	UVM_INFO @ 915541369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	18875705592991928372699706695082884876610213771677578156623664424961521047894	178	UVM_INFO @ 4820419908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	46082483031679345975984188607411707261147253499578793005395101478239386041427	157	UVM_INFO @ 127402817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)				2 test runs
	otbn_stress_all_with_rand_reset	100667034097265291735768183326335255845329738070572847808526911840545785835013	426	UVM_INFO @ 1160851957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	6886332012190834110532232807519469813039231685709344767676696866957140894107	206	UVM_INFO @ 8076658000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				2 test runs
	otbn_escalate	86966153838800484674083300361882089733059005817773949598771798643506424397847	None	~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program) ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize assert bodysize is not None ^^^^^^^^^^^^^^^^^^^^ AssertionError ninja: build stopped: subcommand failed. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
	otbn_illegal_mem_acc	93822670163127838012355184220208570386094263735727616772722023035365974871806	None	~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program) ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize assert bodysize is not None ^^^^^^^^^^^^^^^^^^^^ AssertionError ninja: build stopped: subcommand failed. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
xmsim: E,ASRTST (/nightly/current_run/scratch/reseed_opt/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_/tb.sv,292): Assertion MatchingStatus_A has failed				1 test run
	otbn_partial_wipe	10068330887829655034091254777440623495386256251131045345148745680987022397222	168	UVM_ERROR @ 12519015 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A UVM_INFO @ 12519015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---