TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Monday March 17 2025 20:35:47 UTC

GitHub Revision: d5eebc5dad

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
ADC_CTRL 21 25 84.00
AES/UNMASKED 26 32 81.25
AES/MASKED 26 32 81.25
AON_TIMER 20 23 86.96
CSRNG 16 19 84.21
EDN 18 21 85.71
ENTROPY_SRC 15 22 68.18
HMAC 24 28 85.71
I2C 44 50 88.00
KEYMGR 24 30 80.00
KMAC/MASKED 34 40 85.00
KMAC/UNMASKED 34 40 85.00
LC_CTRL/VOLATILE_UNLOCK_DISABLED 31 39 79.49
LC_CTRL/VOLATILE_UNLOCK_ENABLED 31 39 79.49
OTBN 36 41 87.80
PATTGEN 15 18 83.33
PRIM_ALERT 4 4 100.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
PWM 14 17 82.35
ROM_CTRL/32KB 16 19 84.21
ROM_CTRL/64KB 16 19 84.21
RV_DM/USE_JTAG_INTERFACE 47 53 88.68
RV_TIMER 13 16 81.25
SPI_HOST 24 26 92.31
SPI_DEVICE/1R1W 29 33 87.88
SPI_DEVICE/2P 30 33 90.91
SRAM_CTRL/MAIN 27 31 87.10
SRAM_CTRL/RET 27 31 87.10
SYSRST_CTRL 24 27 88.89
UART 24 27 88.89
USBDEV 95 99 95.96
GPIO 24 27 88.89
ALERT_HANDLER 22 26 84.62
CLKMGR 22 27 81.48
FLASH_CTRL 51 78 65.38
OTP_CTRL 20 30 66.67
PWRMGR 24 29 82.76
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 17 19 89.47
XBAR_MAIN 18 18 100.00
XBAR_PERI 18 18 100.00
CHIP 277 325 85.23