TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Thursday November 06 2025 19:19:18 UTC

GitHub Revision: 8507ebb

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
ADC_CTRL 25 25 100.00
AES/UNMASKED 31 32 96.88
AES/MASKED 31 32 96.88
AON_TIMER 23 23 100.00
CSRNG 19 19 100.00
EDN 21 21 100.00
ENTROPY_SRC/RNG_4BITS 22 22 100.00
HMAC 28 28 100.00
I2C 43 50 86.00
KEYMGR 30 30 100.00
KMAC/MASKED 40 40 100.00
KMAC/UNMASKED 40 40 100.00
LC_CTRL/VOLATILE_UNLOCK_DISABLED 33 39 84.62
LC_CTRL/VOLATILE_UNLOCK_ENABLED 35 39 89.74
OTBN 17 41 41.46
PATTGEN 15 18 83.33
PRIM_ALERT 5 5 100.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 18 19 94.74
ROM_CTRL/64KB 18 19 94.74
RV_DM/USE_JTAG_INTERFACE 46 53 86.79
RV_TIMER 17 19 89.47
SPI_HOST 26 26 100.00
SPI_DEVICE/1R1W 31 33 93.94
SPI_DEVICE/2P 33 33 100.00
SRAM_CTRL/MAIN 30 31 96.77
SRAM_CTRL/RET 30 31 96.77
SYSRST_CTRL 26 27 96.30
UART 26 27 96.30
USBDEV 98 100 98.00
GPIO 26 27 96.30
ALERT_HANDLER 24 26 92.31
CLKMGR 26 27 96.30
FLASH_CTRL 79 79 100.00
OTP_CTRL 27 30 90.00
PWM 17 17 100.00
PWRMGR 25 28 89.29
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 19 19 100.00
XBAR_MAIN 18 18 100.00
XBAR_PERI 18 18 100.00
CHIP 278 326 85.28