TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Monday September 01 2025 16:38:37 UTC

GitHub Revision: 9bb489f

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
ADC_CTRL 25 25 100.00
AES/UNMASKED 31 32 96.88
AES/MASKED 31 32 96.88
AON_TIMER 23 23 100.00
CSRNG 19 19 100.00
EDN 20 21 95.24
ENTROPY_SRC/RNG_4BITS 21 22 95.45
HMAC 28 28 100.00
I2C 44 50 88.00
KEYMGR 29 30 96.67
KMAC/MASKED 40 40 100.00
KMAC/UNMASKED 40 40 100.00
LC_CTRL/VOLATILE_UNLOCK_DISABLED 38 39 97.44
LC_CTRL/VOLATILE_UNLOCK_ENABLED 39 39 100.00
OTBN 40 41 97.56
PATTGEN 16 18 88.89
PRIM_ALERT 4 5 80.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 19 19 100.00
ROM_CTRL/64KB 19 19 100.00
RV_DM/USE_JTAG_INTERFACE 44 53 83.02
RV_TIMER 19 19 100.00
SPI_HOST 25 26 96.15
SPI_DEVICE/1R1W 31 33 93.94
SPI_DEVICE/2P 33 33 100.00
SRAM_CTRL/MAIN 29 31 93.55
SRAM_CTRL/RET 30 31 96.77
SYSRST_CTRL 27 27 100.00
UART 25 27 92.59
USBDEV 98 100 98.00
GPIO 26 27 96.30
ALERT_HANDLER 21 26 80.77
CLKMGR 27 27 100.00
FLASH_CTRL 63 78 80.77
OTP_CTRL 27 30 90.00
PWM 8 17 47.06
PWRMGR 12 28 42.86
RSTMGR_CNSTY_CHK 0 1 0.00
RSTMGR 19 19 100.00
XBAR_MAIN 18 18 100.00
XBAR_PERI 18 18 100.00
CHIP 281 325 86.46