TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Wednesday September 17 2025 00:56:50 UTC

GitHub Revision: c47b886

Branch: master

Name Passing Total Pass Rate
TL_AGENT 0 50 0.00
ADC_CTRL 47 920 5.11
AES/UNMASKED 68 1602 4.24
AES/MASKED 77 1602 4.81
AON_TIMER 25 315 7.94
CSRNG 88 1630 5.40
EDN 62 1130 5.49
ENTROPY_SRC/RNG_4BITS 132 2570 5.14
HMAC 36 821 4.38
I2C 84 2042 4.11
KEYMGR 81 1110 7.30
KMAC/MASKED 0 940 0.00
KMAC/UNMASKED 0 940 0.00
LC_CTRL/VOLATILE_UNLOCK_DISABLED 48 1030 4.66
LC_CTRL/VOLATILE_UNLOCK_ENABLED 55 1030 5.34
OTBN 13 585 2.22
PATTGEN 31 570 5.44
PRIM_ALERT 0 100 0.00
PRIM_ESC 0 20 0.00
PRIM_LFSR 0 200 0.00
PRIM_PRESENT 0 50 0.00
PRIM_PRINCE 0 500 0.00
ROM_CTRL/32KB 14 266 5.26
ROM_CTRL/64KB 9 266 3.38
RV_DM/USE_JTAG_INTERFACE 17 483 3.52
RV_TIMER 14 350 4.00
SPI_HOST 49 840 5.83
SPI_DEVICE/1R1W 51 1151 4.43
SPI_DEVICE/2P 51 1151 4.43
SRAM_CTRL/MAIN 59 1190 4.96
SRAM_CTRL/RET 67 1190 5.63
SYSRST_CTRL 42 932 4.51
UART 69 1320 5.23
USBDEV 201 3970 5.06
GPIO 37 1020 3.63
ALERT_HANDLER 39 850 4.59
CLKMGR 0 960 0.00
FLASH_CTRL 61 1281 4.76
OTP_CTRL 0 1343 0.00
PWM 8 276 2.90
PWRMGR 25 1070 2.34
RSTMGR_CNSTY_CHK 0 10 0.00
RSTMGR 32 620 5.16
XBAR_MAIN 0 900 0.00
XBAR_PERI 0 900 0.00
CHIP 75 2955 2.54