TOP_DARJEELING_BATCH_SIM Simulation Results (Summary)

Wednesday April 02 2025 17:22:48 UTC

GitHub Revision: 688b340

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
AES/UNMASKED 29 32 90.62
AES/MASKED 29 32 90.62
AON_TIMER 23 23 100.00
CSRNG 18 19 94.74
DMA 20 21 95.24
EDN 20 21 95.24
HMAC 28 28 100.00
I2C 45 50 90.00
KEYMGR 26 30 86.67
KEYMGR_DPE 12 14 85.71
KMAC/MASKED 35 40 87.50
KMAC/UNMASKED 37 40 92.50
LC_CTRL/VOLATILE_UNLOCK_DISABLED 38 39 97.44
LC_CTRL/VOLATILE_UNLOCK_ENABLED 38 39 97.44
MBX 11 14 78.57
OTBN 39 41 95.12
PRIM_ALERT 3 4 75.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 19 19 100.00
ROM_CTRL/64KB 19 19 100.00
RV_DM/USE_DMI_INTERFACE 40 53 75.47
RV_TIMER 15 16 93.75
SPI_HOST 25 26 96.15
SPI_DEVICE/1R1W 31 33 93.94
SRAM_CTRL/MAIN 29 31 93.55
SRAM_CTRL/RET 29 31 93.55
UART 27 27 100.00
AC_RANGE_CHECK 10 16 62.50
ALERT_HANDLER 23 26 88.46
GPIO 26 28 92.86
OTP_CTRL 25 30 83.33
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 19 19 100.00
XBAR_MAIN 18 18 100.00
XBAR_PERI 18 18 100.00
XBAR_DBG 18 18 100.00
XBAR_MBX 18 18 100.00
CHIP 73 246 29.67