TOP_DARJEELING_BATCH_SIM Simulation Results (Summary)

Tuesday April 15 2025 17:03:28 UTC

GitHub Revision: 3527f96

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
AES/UNMASKED 30 32 93.75
AES/MASKED 30 32 93.75
AON_TIMER 23 23 100.00
CSRNG 18 19 94.74
DMA 21 21 100.00
EDN 21 21 100.00
HMAC 28 28 100.00
I2C 44 50 88.00
KEYMGR 28 30 93.33
KEYMGR_DPE 14 14 100.00
KMAC/MASKED 40 40 100.00
KMAC/UNMASKED 38 40 95.00
LC_CTRL/VOLATILE_UNLOCK_DISABLED 39 39 100.00
LC_CTRL/VOLATILE_UNLOCK_ENABLED 39 39 100.00
MBX 11 14 78.57
OTBN 40 41 97.56
PRIM_ALERT 4 4 100.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 18 19 94.74
ROM_CTRL/64KB 19 19 100.00
RV_DM/USE_DMI_INTERFACE 40 53 75.47
RV_TIMER 15 16 93.75
SPI_HOST 26 26 100.00
SPI_DEVICE/1R1W 31 33 93.94
SRAM_CTRL/MAIN 29 31 93.55
SRAM_CTRL/RET 30 31 96.77
UART 27 27 100.00
AC_RANGE_CHECK 11 16 68.75
ALERT_HANDLER 24 26 92.31
CLKMGR 23 27 85.19
GPIO 27 28 96.43
OTP_CTRL 26 30 86.67
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 19 19 100.00
XBAR_MAIN 18 18 100.00
XBAR_PERI 18 18 100.00
XBAR_DBG 18 18 100.00
XBAR_MBX 18 18 100.00
CHIP 76 247 30.77