TOP_DARJEELING_BATCH_SIM Simulation Results (Summary)

Thursday April 17 2025 17:08:19 UTC

GitHub Revision: 91d1222

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
AES/UNMASKED 31 32 96.88
AES/MASKED 31 32 96.88
AON_TIMER 23 23 100.00
CSRNG 18 19 94.74
DMA 21 21 100.00
EDN 21 21 100.00
HMAC 28 28 100.00
I2C 44 50 88.00
KEYMGR 29 30 96.67
KEYMGR_DPE 14 14 100.00
KMAC/MASKED 40 40 100.00
KMAC/UNMASKED 38 40 95.00
LC_CTRL/VOLATILE_UNLOCK_DISABLED 38 39 97.44
LC_CTRL/VOLATILE_UNLOCK_ENABLED 39 39 100.00
MBX 10 14 71.43
OTBN 39 41 95.12
PRIM_ALERT 4 4 100.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 19 19 100.00
ROM_CTRL/64KB 19 19 100.00
RV_DM/USE_DMI_INTERFACE 40 53 75.47
RV_TIMER 15 16 93.75
SPI_HOST 25 26 96.15
SPI_DEVICE/1R1W 31 33 93.94
SRAM_CTRL/MAIN 28 31 90.32
SRAM_CTRL/RET 30 31 96.77
UART 27 27 100.00
AC_RANGE_CHECK 11 16 68.75
ALERT_HANDLER 20 26 76.92
CLKMGR 26 27 96.30
GPIO 25 28 89.29
OTP_CTRL 28 30 93.33
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 19 19 100.00
XBAR_MAIN 18 18 100.00
XBAR_PERI 18 18 100.00
XBAR_DBG 18 18 100.00
XBAR_MBX 18 18 100.00
CHIP 77 247 31.17