TOP_DARJEELING_BATCH_SIM Simulation Results (Summary)

Monday September 15 2025 16:25:37 UTC

GitHub Revision: cf445d0

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
AES/UNMASKED 1 32 3.12
AES/MASKED 1 32 3.12
AON_TIMER 17 23 73.91
CSRNG 1 19 5.26
DMA 1 25 4.00
EDN 21 21 100.00
ENTROPY_SRC/RNG_16BITS 3 22 13.64
HMAC 27 28 96.43
I2C 39 50 78.00
KEYMGR 28 30 93.33
KEYMGR_DPE 13 14 92.86
KMAC/MASKED 0 40 0.00
KMAC/UNMASKED 24 40 60.00
LC_CTRL/VOLATILE_UNLOCK_DISABLED 35 39 89.74
LC_CTRL/VOLATILE_UNLOCK_ENABLED 32 39 82.05
MBX 2 16 12.50
OTBN 0 41 0.00
PRIM_ALERT 5 5 100.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 15 19 78.95
ROM_CTRL/64KB 15 19 78.95
RV_DM/USE_DMI_INTERFACE 34 53 64.15
RV_TIMER 17 19 89.47
SPI_HOST 2 26 7.69
SPI_DEVICE/1R1W 9 33 27.27
SRAM_CTRL/MAIN 28 31 90.32
SRAM_CTRL/RET 29 31 93.55
UART 9 27 33.33
AC_RANGE_CHECK 2 20 10.00
ALERT_HANDLER 13 26 50.00
CLKMGR 26 27 96.30
GPIO 16 28 57.14
OTP_CTRL 20 30 66.67
RSTMGR_CNSTY_CHK 0 1 0.00
RSTMGR 17 19 89.47
XBAR_MAIN 17 18 94.44
XBAR_PERI 15 18 83.33
XBAR_DBG 16 18 88.89
XBAR_MBX 15 18 83.33
CHIP 1 250 0.40