TOP_DARJEELING_BATCH_SIM Simulation Results (Summary)

Monday September 22 2025 16:09:37 UTC

GitHub Revision: 359e412

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
AES/UNMASKED 2 32 6.25
AES/MASKED 3 32 9.38
AON_TIMER 0 23 0.00
CSRNG 1 19 5.26
DMA 3 25 12.00
EDN 20 21 95.24
ENTROPY_SRC/RNG_16BITS 1 22 4.55
HMAC 17 28 60.71
I2C 36 50 72.00
KEYMGR 29 30 96.67
KEYMGR_DPE 3 14 21.43
KMAC/MASKED 38 40 95.00
KMAC/UNMASKED 10 40 25.00
LC_CTRL/VOLATILE_UNLOCK_DISABLED 22 39 56.41
LC_CTRL/VOLATILE_UNLOCK_ENABLED 15 39 38.46
MBX 0 16 0.00
OTBN 0 41 0.00
PRIM_ALERT 4 5 80.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 3 4 75.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 16 19 84.21
ROM_CTRL/64KB 17 19 89.47
RV_DM/USE_DMI_INTERFACE 33 53 62.26
RV_TIMER 14 19 73.68
SPI_HOST 0 26 0.00
SPI_DEVICE/1R1W 29 33 87.88
SRAM_CTRL/MAIN 27 31 87.10
SRAM_CTRL/RET 27 31 87.10
UART 8 27 29.63
AC_RANGE_CHECK 1 20 5.00
ALERT_HANDLER 23 26 88.46
CLKMGR 23 27 85.19
GPIO 24 28 85.71
OTP_CTRL 18 30 60.00
RSTMGR_CNSTY_CHK 0 1 0.00
RSTMGR 16 19 84.21
XBAR_MAIN 16 18 88.89
XBAR_PERI 17 18 94.44
XBAR_DBG 17 18 94.44
XBAR_MBX 17 18 94.44
CHIP 2 250 0.80