TOP_DARJEELING_BATCH_SIM Simulation Results (Summary)

Wednesday November 05 2025 16:07:17 UTC

GitHub Revision: 9baed2b

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
AES/UNMASKED 31 32 96.88
AES/MASKED 31 32 96.88
AON_TIMER 23 23 100.00
CSRNG 19 19 100.00
DMA 24 25 96.00
EDN 20 21 95.24
ENTROPY_SRC/RNG_16BITS 22 22 100.00
HMAC 28 28 100.00
I2C 45 50 90.00
KEYMGR 30 30 100.00
KEYMGR_DPE 14 14 100.00
KMAC/MASKED 40 40 100.00
KMAC/UNMASKED 38 40 95.00
LC_CTRL/VOLATILE_UNLOCK_DISABLED 33 39 84.62
LC_CTRL/VOLATILE_UNLOCK_ENABLED 34 39 87.18
MBX 16 16 100.00
OTBN 19 41 46.34
PRIM_ALERT 4 5 80.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 18 19 94.74
ROM_CTRL/64KB 19 19 100.00
RV_DM/USE_DMI_INTERFACE 40 53 75.47
RV_TIMER 16 19 84.21
SPI_HOST 26 26 100.00
SPI_DEVICE/1R1W 31 33 93.94
SRAM_CTRL/MAIN 30 31 96.77
SRAM_CTRL/RET 30 31 96.77
UART 26 27 96.30
AC_RANGE_CHECK 19 20 95.00
ALERT_HANDLER 25 26 96.15
CLKMGR 9 22 40.91
GPIO 27 28 96.43
OTP_CTRL 17 30 56.67
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 19 19 100.00
XBAR_MAIN 18 18 100.00
XBAR_PERI 18 18 100.00
XBAR_DBG 18 18 100.00
XBAR_MBX 18 18 100.00
CHIP 81 250 32.40