TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Tuesday September 16 2025 20:21:12 UTC

GitHub Revision: f6ac363

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
ADC_CTRL 0 25 0.00
AES/UNMASKED 1 32 3.12
AES/MASKED 0 32 0.00
AON_TIMER 19 23 82.61
CSRNG 1 19 5.26
EDN 10 21 47.62
ENTROPY_SRC/RNG_4BITS 0 22 0.00
HMAC 27 28 96.43
I2C 39 50 78.00
KEYMGR 29 30 96.67
KMAC/MASKED 37 40 92.50
KMAC/UNMASKED 0 40 0.00
LC_CTRL/VOLATILE_UNLOCK_DISABLED 23 39 58.97
LC_CTRL/VOLATILE_UNLOCK_ENABLED 37 39 94.87
OTBN 3 41 7.32
PATTGEN 4 18 22.22
PRIM_ALERT 4 5 80.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 16 19 84.21
ROM_CTRL/64KB 18 19 94.74
RV_DM/USE_JTAG_INTERFACE 41 53 77.36
RV_TIMER 8 19 42.11
SPI_HOST 2 26 7.69
SPI_DEVICE/1R1W 29 33 87.88
SPI_DEVICE/2P 10 33 30.30
SRAM_CTRL/MAIN 27 31 87.10
SRAM_CTRL/RET 27 31 87.10
SYSRST_CTRL 24 27 88.89
UART 8 27 29.63
USBDEV 93 100 93.00
GPIO 25 27 92.59
ALERT_HANDLER 22 26 84.62
CLKMGR 26 27 96.30
FLASH_CTRL 49 78 62.82
OTP_CTRL 15 30 50.00
PWM 1 17 5.88
PWRMGR 14 28 50.00
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 10 19 52.63
XBAR_MAIN 18 18 100.00
XBAR_PERI 15 18 83.33
CHIP 49 325 15.08