TOP_DARJEELING_BATCH_SIM Simulation Results (Summary)

Monday April 28 2025 17:09:10 UTC

GitHub Revision: 841f73f

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
AES/UNMASKED 31 32 96.88
AES/MASKED 31 32 96.88
AON_TIMER 23 23 100.00
CSRNG 18 19 94.74
DMA 21 21 100.00
EDN 20 21 95.24
HMAC 28 28 100.00
I2C 46 50 92.00
KEYMGR 27 30 90.00
KEYMGR_DPE 14 14 100.00
KMAC/MASKED 39 40 97.50
KMAC/UNMASKED 39 40 97.50
LC_CTRL/VOLATILE_UNLOCK_DISABLED 38 39 97.44
LC_CTRL/VOLATILE_UNLOCK_ENABLED 39 39 100.00
MBX 11 14 78.57
OTBN 39 41 95.12
PRIM_ALERT 4 4 100.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 18 19 94.74
ROM_CTRL/64KB 18 19 94.74
RV_DM/USE_DMI_INTERFACE 41 53 77.36
RV_TIMER 16 16 100.00
SPI_HOST 25 26 96.15
SPI_DEVICE/1R1W 31 33 93.94
SRAM_CTRL/MAIN 29 31 93.55
SRAM_CTRL/RET 29 31 93.55
UART 27 27 100.00
AC_RANGE_CHECK 11 16 68.75
ALERT_HANDLER 22 26 84.62
CLKMGR 25 27 92.59
GPIO 27 28 96.43
OTP_CTRL 28 30 93.33
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 19 19 100.00
XBAR_MAIN 18 18 100.00
XBAR_PERI 18 18 100.00
XBAR_DBG 18 18 100.00
XBAR_MBX 18 18 100.00
CHIP 76 247 30.77