TOP_DARJEELING_BATCH_SIM Simulation Results (Summary)

Tuesday September 16 2025 16:05:40 UTC

GitHub Revision: 572e2c3

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
AES/UNMASKED 3 32 9.38
AES/MASKED 6 32 18.75
AON_TIMER 22 23 95.65
CSRNG 1 19 5.26
DMA 1 25 4.00
EDN 10 21 47.62
ENTROPY_SRC/RNG_16BITS 2 22 9.09
HMAC 26 28 92.86
I2C 9 50 18.00
KEYMGR 29 30 96.67
KEYMGR_DPE 14 14 100.00
KMAC/MASKED 38 40 95.00
KMAC/UNMASKED 33 40 82.50
LC_CTRL/VOLATILE_UNLOCK_DISABLED 36 39 92.31
LC_CTRL/VOLATILE_UNLOCK_ENABLED 38 39 97.44
MBX 1 16 6.25
OTBN 3 41 7.32
PRIM_ALERT 4 5 80.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 0 1 0.00
ROM_CTRL/32KB 17 19 89.47
ROM_CTRL/64KB 16 19 84.21
RV_DM/USE_DMI_INTERFACE 39 53 73.58
RV_TIMER 19 19 100.00
SPI_HOST 0 26 0.00
SPI_DEVICE/1R1W 28 33 84.85
SRAM_CTRL/MAIN 29 31 93.55
SRAM_CTRL/RET 25 31 80.65
UART 23 27 85.19
AC_RANGE_CHECK 0 20 0.00
ALERT_HANDLER 22 26 84.62
CLKMGR 21 27 77.78
GPIO 26 28 92.86
OTP_CTRL 20 30 66.67
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 19 19 100.00
XBAR_MAIN 17 18 94.44
XBAR_PERI 18 18 100.00
XBAR_DBG 16 18 88.89
XBAR_MBX 0 18 0.00
CHIP 17 250 6.80