TOP_DARJEELING_BATCH_SIM Simulation Results (Summary)

Tuesday October 07 2025 16:07:43 UTC

GitHub Revision: 0f6fcf0

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
AES/UNMASKED 31 32 96.88
AES/MASKED 31 32 96.88
AON_TIMER 23 23 100.00
CSRNG 18 19 94.74
DMA 24 25 96.00
EDN 20 21 95.24
ENTROPY_SRC/RNG_16BITS 22 22 100.00
HMAC 28 28 100.00
I2C 43 50 86.00
KEYMGR 30 30 100.00
KEYMGR_DPE 14 14 100.00
KMAC/MASKED 39 40 97.50
KMAC/UNMASKED 39 40 97.50
LC_CTRL/VOLATILE_UNLOCK_DISABLED 39 39 100.00
LC_CTRL/VOLATILE_UNLOCK_ENABLED 39 39 100.00
MBX 14 16 87.50
OTBN 20 41 48.78
PRIM_ALERT 3 5 60.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 18 19 94.74
ROM_CTRL/64KB 19 19 100.00
RV_DM/USE_DMI_INTERFACE 39 53 73.58
RV_TIMER 16 19 84.21
SPI_HOST 26 26 100.00
SPI_DEVICE/1R1W 31 33 93.94
SRAM_CTRL/MAIN 29 31 93.55
SRAM_CTRL/RET 30 31 96.77
UART 26 27 96.30
AC_RANGE_CHECK 20 20 100.00
ALERT_HANDLER 25 26 96.15
CLKMGR 25 27 92.59
GPIO 27 28 96.43
OTP_CTRL 21 30 70.00
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 19 19 100.00
XBAR_MAIN 17 18 94.44
XBAR_PERI 18 18 100.00
XBAR_DBG 18 18 100.00
XBAR_MBX 18 18 100.00
CHIP 76 250 30.40