TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Wednesday September 03 2025 16:00:25 UTC

GitHub Revision: 83b8114

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
ADC_CTRL 25 25 100.00
AES/UNMASKED 31 32 96.88
AES/MASKED 30 32 93.75
AON_TIMER 23 23 100.00
CSRNG 19 19 100.00
EDN 21 21 100.00
ENTROPY_SRC/RNG_4BITS 20 22 90.91
HMAC 28 28 100.00
I2C 43 50 86.00
KEYMGR 30 30 100.00
KMAC/MASKED 40 40 100.00
KMAC/UNMASKED 39 40 97.50
LC_CTRL/VOLATILE_UNLOCK_DISABLED 39 39 100.00
LC_CTRL/VOLATILE_UNLOCK_ENABLED 39 39 100.00
OTBN 40 41 97.56
PATTGEN 16 18 88.89
PRIM_ALERT 5 5 100.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 18 19 94.74
ROM_CTRL/64KB 19 19 100.00
RV_DM/USE_JTAG_INTERFACE 44 53 83.02
RV_TIMER 19 19 100.00
SPI_HOST 26 26 100.00
SPI_DEVICE/1R1W 31 33 93.94
SPI_DEVICE/2P 33 33 100.00
SRAM_CTRL/MAIN 29 31 93.55
SRAM_CTRL/RET 30 31 96.77
SYSRST_CTRL 27 27 100.00
UART 26 27 96.30
USBDEV 98 100 98.00
GPIO 26 27 96.30
ALERT_HANDLER 22 26 84.62
CLKMGR 26 27 96.30
FLASH_CTRL 60 78 76.92
OTP_CTRL 27 30 90.00
PWM 8 17 47.06
PWRMGR 11 28 39.29
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 19 19 100.00
XBAR_MAIN 18 18 100.00
XBAR_PERI 18 18 100.00
CHIP 283 325 87.08