TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Wednesday October 01 2025 17:16:06 UTC

GitHub Revision: f8e4a6c

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
ADC_CTRL 25 25 100.00
AES/UNMASKED 31 32 96.88
AES/MASKED 31 32 96.88
AON_TIMER 23 23 100.00
CSRNG 19 19 100.00
EDN 21 21 100.00
ENTROPY_SRC/RNG_4BITS 22 22 100.00
HMAC 28 28 100.00
I2C 42 50 84.00
KEYMGR 29 30 96.67
KMAC/MASKED 40 40 100.00
KMAC/UNMASKED 40 40 100.00
LC_CTRL/VOLATILE_UNLOCK_DISABLED 37 39 94.87
LC_CTRL/VOLATILE_UNLOCK_ENABLED 39 39 100.00
OTBN 17 41 41.46
PATTGEN 16 18 88.89
PRIM_ALERT 4 5 80.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 17 19 89.47
ROM_CTRL/64KB 18 19 94.74
RV_DM/USE_JTAG_INTERFACE 45 53 84.91
RV_TIMER 16 19 84.21
SPI_HOST 26 26 100.00
SPI_DEVICE/1R1W 31 33 93.94
SPI_DEVICE/2P 33 33 100.00
SRAM_CTRL/MAIN 30 31 96.77
SRAM_CTRL/RET 29 31 93.55
SYSRST_CTRL 25 27 92.59
UART 27 27 100.00
USBDEV 98 100 98.00
GPIO 26 27 96.30
ALERT_HANDLER 24 26 92.31
CLKMGR 26 27 96.30
FLASH_CTRL 61 78 78.21
OTP_CTRL 29 30 96.67
PWM 8 17 47.06
PWRMGR 10 28 35.71
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 19 19 100.00
XBAR_MAIN 18 18 100.00
XBAR_PERI 18 18 100.00
CHIP 281 326 86.20