TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Monday September 15 2025 00:04:07 UTC

GitHub Revision: c127aed

Branch: master

Name Passing Total Pass Rate
TL_AGENT 0 1 0.00
ADC_CTRL 21 25 84.00
AES/UNMASKED 31 32 96.88
AES/MASKED 31 32 96.88
AON_TIMER 23 23 100.00
CSRNG 19 19 100.00
EDN 20 21 95.24
ENTROPY_SRC/RNG_4BITS 22 22 100.00
HMAC 28 28 100.00
I2C 35 50 70.00
KEYMGR 20 30 66.67
KMAC/MASKED 0 40 0.00
KMAC/UNMASKED 0 40 0.00
LC_CTRL/VOLATILE_UNLOCK_DISABLED 38 39 97.44
LC_CTRL/VOLATILE_UNLOCK_ENABLED 39 39 100.00
OTBN 17 41 41.46
PATTGEN 16 18 88.89
PRIM_ALERT 0 5 0.00
PRIM_ESC 0 1 0.00
PRIM_LFSR 0 4 0.00
PRIM_PRESENT 0 1 0.00
PRIM_PRINCE 0 1 0.00
ROM_CTRL/32KB 18 19 94.74
ROM_CTRL/64KB 18 19 94.74
RV_DM/USE_JTAG_INTERFACE 44 53 83.02
RV_TIMER 14 19 73.68
SPI_HOST 26 26 100.00
SPI_DEVICE/1R1W 31 33 93.94
SPI_DEVICE/2P 33 33 100.00
SRAM_CTRL/MAIN 29 31 93.55
SRAM_CTRL/RET 29 31 93.55
SYSRST_CTRL 26 27 96.30
UART 26 27 96.30
USBDEV 98 100 98.00
GPIO 19 27 70.37
ALERT_HANDLER 20 26 76.92
CLKMGR 0 27 0.00
FLASH_CTRL 58 78 74.36
OTP_CTRL 0 30 0.00
PWM 8 17 47.06
PWRMGR 12 28 42.86
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 19 19 100.00
XBAR_MAIN 0 18 0.00
XBAR_PERI 0 18 0.00
CHIP 193 325 59.38