TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Sunday December 07 2025 00:12:41 UTC

GitHub Revision: 9ce72b8

Branch: master

Name	Passing	Total	Pass Rate	Coverage
TL_AGENT	50	50	100.00	--
ADC_CTRL	898	920	97.61	97.38
AES/UNMASKED	3106	3204	96.94	97.16
AES/MASKED	3106	3204	96.94	98.34
AON_TIMER	315	315	100.00	98.65
CSRNG	1628	1630	99.88	97.65
EDN/EDN0	0	2260	0.00	--
EDN/EDN1	0	2260	0.00	--
ENTROPY_SRC/RNG_4BITS	2520	2570	98.05	94.14
HMAC	821	821	100.00	99.17
I2C	1793	2042	87.81	86.21
KEYMGR	1084	1110	97.66	97.67
KMAC/MASKED	1861	1880	98.99	95.15
KMAC/UNMASKED	1861	1880	98.99	93.55
LC_CTRL/VOLATILE_UNLOCK_DISABLED	1672	2060	81.17	89.57
LC_CTRL/VOLATILE_UNLOCK_ENABLED	1672	2060	81.17	89.82
OTBN	568	585	97.09	99.01
PATTGEN	458	570	80.35	98.53
PRIM_ALERT	97	100	97.00	95.19
PRIM_ESC	20	20	100.00	92.29
PRIM_LFSR	200	200	100.00	98.31
PRIM_PRESENT	50	50	100.00	93.41
PRIM_PRINCE	500	500	100.00	100.00
ROM_CTRL/32KB	522	532	98.12	99.12
ROM_CTRL/64KB	522	532	98.12	99.12
RV_DM/USE_JTAG_INTERFACE	342	483	70.81	82.42
RV_TIMER	309	350	88.29	99.47
SPI_HOST	836	840	99.52	96.17
SPI_DEVICE/1R1W	2274	2302	98.78	94.38
SPI_DEVICE/2P	2274	2302	98.78	95.01
SRAM_CTRL/MAIN	2330	2380	97.90	96.41
SRAM_CTRL/RET	2330	2380	97.90	96.39
SYSRST_CTRL	896	932	96.14	97.01
UART	1247	1320	94.47	97.35
USBDEV	3910	3970	98.49	96.79
GPIO	970	1020	95.10	98.32
ALERT_HANDLER	769	850	90.47	98.85
CLKMGR	953	960	99.27	96.95
FLASH_CTRL	1274	1284	99.22	96.27
OTP_CTRL	1120	1343	83.40	87.64
PWM	276	276	100.00	98.88
PWRMGR	928	1070	86.73	95.30
RSTMGR_CNSTY_CHK	10	10	100.00	95.87
RSTMGR	620	620	100.00	99.27
XBAR_MAIN	900	900	100.00	99.08
XBAR_PERI	900	900	100.00	99.05
CHIP	2722	2956	92.08	89.68