TOP_DARJEELING_BATCH_SIM Simulation Results (Summary)

Tuesday September 23 2025 16:10:41 UTC

GitHub Revision: 4330c70

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
AES/UNMASKED 3 32 9.38
AES/MASKED 1 32 3.12
AON_TIMER 10 23 43.48
CSRNG 1 19 5.26
DMA 3 25 12.00
EDN 19 21 90.48
ENTROPY_SRC/RNG_16BITS 3 22 13.64
HMAC 27 28 96.43
I2C 7 50 14.00
KEYMGR 0 30 0.00
KEYMGR_DPE 13 14 92.86
KMAC/MASKED 25 40 62.50
KMAC/UNMASKED 39 40 97.50
LC_CTRL/VOLATILE_UNLOCK_DISABLED 38 39 97.44
LC_CTRL/VOLATILE_UNLOCK_ENABLED 13 39 33.33
MBX 0 16 0.00
OTBN 1 41 2.44
PRIM_ALERT 3 5 60.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 2 4 50.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 19 19 100.00
ROM_CTRL/64KB 15 19 78.95
RV_DM/USE_DMI_INTERFACE 0 53 0.00
RV_TIMER 16 19 84.21
SPI_HOST 3 26 11.54
SPI_DEVICE/1R1W 30 33 90.91
SRAM_CTRL/MAIN 29 31 93.55
SRAM_CTRL/RET 29 31 93.55
UART 24 27 88.89
AC_RANGE_CHECK 0 20 0.00
ALERT_HANDLER 21 26 80.77
CLKMGR 24 27 88.89
GPIO 10 28 35.71
OTP_CTRL 17 30 56.67
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 19 19 100.00
XBAR_MAIN 15 18 83.33
XBAR_PERI 17 18 94.44
XBAR_DBG 16 18 88.89
XBAR_MBX 18 18 100.00
CHIP 17 250 6.80