TOP_DARJEELING_BATCH_SIM Simulation Results (Summary)

Monday November 03 2025 16:06:17 UTC

GitHub Revision: 2c4c18b

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
AES/UNMASKED 29 32 90.62
AES/MASKED 31 32 96.88
AON_TIMER 23 23 100.00
CSRNG 19 19 100.00
DMA 24 25 96.00
EDN 21 21 100.00
ENTROPY_SRC/RNG_16BITS 22 22 100.00
HMAC 28 28 100.00
I2C 40 50 80.00
KEYMGR 30 30 100.00
KEYMGR_DPE 14 14 100.00
KMAC/MASKED 39 40 97.50
KMAC/UNMASKED 39 40 97.50
LC_CTRL/VOLATILE_UNLOCK_DISABLED 34 39 87.18
LC_CTRL/VOLATILE_UNLOCK_ENABLED 34 39 87.18
MBX 14 16 87.50
OTBN 21 41 51.22
PRIM_ALERT 5 5 100.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 17 19 89.47
ROM_CTRL/64KB 18 19 94.74
RV_DM/USE_DMI_INTERFACE 41 53 77.36
RV_TIMER 15 19 78.95
SPI_HOST 26 26 100.00
SPI_DEVICE/1R1W 31 33 93.94
SRAM_CTRL/MAIN 30 31 96.77
SRAM_CTRL/RET 30 31 96.77
UART 26 27 96.30
AC_RANGE_CHECK 19 20 95.00
ALERT_HANDLER 24 26 92.31
CLKMGR 12 22 54.55
GPIO 26 28 92.86
OTP_CTRL 17 30 56.67
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 19 19 100.00
XBAR_MAIN 17 18 94.44
XBAR_PERI 18 18 100.00
XBAR_DBG 18 18 100.00
XBAR_MBX 18 18 100.00
CHIP 78 250 31.20