TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Thursday September 25 2025 19:17:05 UTC

GitHub Revision: 8f374b4

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
ADC_CTRL 25 25 100.00
AES/UNMASKED 31 32 96.88
AES/MASKED 31 32 96.88
AON_TIMER 23 23 100.00
CSRNG 19 19 100.00
EDN 20 21 95.24
ENTROPY_SRC/RNG_4BITS 22 22 100.00
HMAC 28 28 100.00
I2C 43 50 86.00
KEYMGR 28 30 93.33
KMAC/MASKED 39 40 97.50
KMAC/UNMASKED 38 40 95.00
LC_CTRL/VOLATILE_UNLOCK_DISABLED 38 39 97.44
LC_CTRL/VOLATILE_UNLOCK_ENABLED 38 39 97.44
OTBN 19 41 46.34
PATTGEN 16 18 88.89
PRIM_ALERT 5 5 100.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 19 19 100.00
ROM_CTRL/64KB 18 19 94.74
RV_DM/USE_JTAG_INTERFACE 44 53 83.02
RV_TIMER 17 19 89.47
SPI_HOST 26 26 100.00
SPI_DEVICE/1R1W 31 33 93.94
SPI_DEVICE/2P 33 33 100.00
SRAM_CTRL/MAIN 30 31 96.77
SRAM_CTRL/RET 29 31 93.55
SYSRST_CTRL 26 27 96.30
UART 25 27 92.59
USBDEV 98 100 98.00
GPIO 26 27 96.30
ALERT_HANDLER 23 26 88.46
CLKMGR 26 27 96.30
FLASH_CTRL 57 78 73.08
OTP_CTRL 27 30 90.00
PWM 8 17 47.06
PWRMGR 16 28 57.14
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 19 19 100.00
XBAR_MAIN 18 18 100.00
XBAR_PERI 18 18 100.00
CHIP 287 326 88.04