TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Monday November 03 2025 17:34:39 UTC

GitHub Revision: 7f2e68c

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
ADC_CTRL 25 25 100.00
AES/UNMASKED 30 32 93.75
AES/MASKED 31 32 96.88
AON_TIMER 23 23 100.00
CSRNG 19 19 100.00
EDN 20 21 95.24
ENTROPY_SRC/RNG_4BITS 21 22 95.45
HMAC 28 28 100.00
I2C 42 50 84.00
KEYMGR 29 30 96.67
KMAC/MASKED 40 40 100.00
KMAC/UNMASKED 38 40 95.00
LC_CTRL/VOLATILE_UNLOCK_DISABLED 34 39 87.18
LC_CTRL/VOLATILE_UNLOCK_ENABLED 33 39 84.62
OTBN 20 41 48.78
PATTGEN 15 18 83.33
PRIM_ALERT 5 5 100.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 18 19 94.74
ROM_CTRL/64KB 18 19 94.74
RV_DM/USE_JTAG_INTERFACE 45 53 84.91
RV_TIMER 16 19 84.21
SPI_HOST 26 26 100.00
SPI_DEVICE/1R1W 31 33 93.94
SPI_DEVICE/2P 33 33 100.00
SRAM_CTRL/MAIN 30 31 96.77
SRAM_CTRL/RET 30 31 96.77
SYSRST_CTRL 27 27 100.00
UART 25 27 92.59
USBDEV 98 100 98.00
GPIO 26 27 96.30
ALERT_HANDLER 25 26 96.15
CLKMGR 26 27 96.30
FLASH_CTRL 76 79 96.20
OTP_CTRL 27 30 90.00
PWM 8 17 47.06
PWRMGR 24 28 85.71
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 19 19 100.00
XBAR_MAIN 18 18 100.00
XBAR_PERI 18 18 100.00
CHIP 271 326 83.13