TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Sunday November 23 2025 00:12:22 UTC

GitHub Revision: 1f7db17

Branch: master

Name Passing Total Pass Rate Coverage
TL_AGENT 50 50 100.00 --
ADC_CTRL 900 920 97.83 97.35
AES/UNMASKED 3095 3204 96.60 97.23
AES/MASKED 3095 3204 96.60 98.39
AON_TIMER 315 315 100.00 98.65
CSRNG 1630 1630 100.00 97.53
EDN 1116 1130 98.76 95.64
ENTROPY_SRC/RNG_4BITS 2555 2570 99.42 94.20
HMAC 821 821 100.00 99.18
I2C 1781 2042 87.22 85.87
KEYMGR 1084 1110 97.66 97.68
KMAC/MASKED 1860 1880 98.94 95.45
KMAC/UNMASKED 1860 1880 98.94 93.68
LC_CTRL/VOLATILE_UNLOCK_DISABLED 1684 2060 81.75 89.70
LC_CTRL/VOLATILE_UNLOCK_ENABLED 1684 2060 81.75 89.81
OTBN 562 585 96.07 99.05
PATTGEN 447 570 78.42 98.53
PRIM_ALERT 95 100 95.00 95.19
PRIM_ESC 20 20 100.00 92.29
PRIM_LFSR 200 200 100.00 98.31
PRIM_PRESENT 50 50 100.00 93.41
PRIM_PRINCE 500 500 100.00 100.00
ROM_CTRL/32KB 518 532 97.37 98.29
ROM_CTRL/64KB 518 532 97.37 98.29
RV_DM/USE_JTAG_INTERFACE 342 483 70.81 77.47
RV_TIMER 305 350 87.14 99.32
SPI_HOST 836 840 99.52 96.16
SPI_DEVICE/1R1W 2278 2302 98.96 94.38
SPI_DEVICE/2P 2278 2302 98.96 95.01
SRAM_CTRL/MAIN 2321 2380 97.52 96.36
SRAM_CTRL/RET 2321 2380 97.52 96.36
SYSRST_CTRL 902 932 96.78 96.91
UART 1258 1320 95.30 97.33
USBDEV 3909 3970 98.46 97.06
GPIO 970 1020 95.10 98.32
ALERT_HANDLER 781 850 91.88 98.84
CLKMGR 953 960 99.27 97.01
FLASH_CTRL 1266 1284 98.60 96.28
OTP_CTRL 1121 1343 83.47 87.65
PWM 275 276 99.64 98.61
PWRMGR 972 1070 90.84 95.32
RSTMGR_CNSTY_CHK 9 10 90.00 95.87
RSTMGR 620 620 100.00 99.25
XBAR_MAIN 900 900 100.00 99.00
XBAR_PERI 900 900 100.00 99.01
CHIP 2727 2956 92.25 89.73