TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Sunday November 30 2025 00:07:20 UTC

GitHub Revision: c766185

Branch: master

Name Passing Total Pass Rate Coverage
TL_AGENT 50 50 100.00 --
ADC_CTRL 895 920 97.28 97.36
AES/UNMASKED 3100 3204 96.75 97.26
AES/MASKED 3100 3204 96.75 98.36
AON_TIMER 315 315 100.00 98.65
CSRNG 1628 1630 99.88 97.51
EDN 1130 1130 100.00 95.57
ENTROPY_SRC/RNG_4BITS 2552 2570 99.30 94.18
HMAC 821 821 100.00 99.17
I2C 1795 2042 87.90 86.22
KEYMGR 1083 1110 97.57 97.60
KMAC/MASKED 1859 1880 98.88 95.23
KMAC/UNMASKED 1859 1880 98.88 93.65
LC_CTRL/VOLATILE_UNLOCK_DISABLED 1677 2060 81.41 89.90
LC_CTRL/VOLATILE_UNLOCK_ENABLED 1677 2060 81.41 89.61
OTBN 566 585 96.75 99.02
PATTGEN 457 570 80.18 98.53
PRIM_ALERT 94 100 94.00 95.19
PRIM_ESC 20 20 100.00 92.29
PRIM_LFSR 200 200 100.00 98.31
PRIM_PRESENT 50 50 100.00 93.41
PRIM_PRINCE 500 500 100.00 100.00
ROM_CTRL/32KB 523 532 98.31 99.12
ROM_CTRL/64KB 523 532 98.31 98.29
RV_DM/USE_JTAG_INTERFACE 341 483 70.60 81.42
RV_TIMER 307 350 87.71 99.22
SPI_HOST 838 840 99.76 96.19
SPI_DEVICE/1R1W 2279 2302 99.00 94.38
SPI_DEVICE/2P 2279 2302 99.00 95.00
SRAM_CTRL/MAIN 2325 2380 97.69 96.39
SRAM_CTRL/RET 2325 2380 97.69 96.42
SYSRST_CTRL 907 932 97.32 96.01
UART 1257 1320 95.23 97.34
USBDEV 3910 3970 98.49 97.03
GPIO 970 1020 95.10 98.32
ALERT_HANDLER 775 850 91.18 98.85
CLKMGR 955 960 99.48 97.05
FLASH_CTRL 1264 1284 98.44 96.34
OTP_CTRL 1138 1343 84.74 87.77
PWM 276 276 100.00 99.10
PWRMGR 972 1070 90.84 95.32
RSTMGR_CNSTY_CHK 7 10 70.00 95.87
RSTMGR 620 620 100.00 99.25
XBAR_MAIN 900 900 100.00 98.99
XBAR_PERI 900 900 100.00 99.00
CHIP 2727 2956 92.25 89.65