TOP_DARJEELING_BATCH_SIM Simulation Results (Summary)

Monday June 16 2025 17:01:07 UTC

GitHub Revision: c0fece9

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
AES/UNMASKED 31 32 96.88
AES/MASKED 31 32 96.88
AON_TIMER 23 23 100.00
CSRNG 18 19 94.74
DMA 21 21 100.00
EDN 21 21 100.00
HMAC 28 28 100.00
I2C 47 50 94.00
KEYMGR 27 30 90.00
KEYMGR_DPE 14 14 100.00
KMAC/MASKED 38 40 95.00
KMAC/UNMASKED 39 40 97.50
LC_CTRL/VOLATILE_UNLOCK_DISABLED 38 39 97.44
LC_CTRL/VOLATILE_UNLOCK_ENABLED 38 39 97.44
MBX 11 14 78.57
OTBN 37 41 90.24
PRIM_ALERT 4 4 100.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 19 19 100.00
ROM_CTRL/64KB 19 19 100.00
RV_DM/USE_DMI_INTERFACE 40 53 75.47
RV_TIMER 19 19 100.00
SPI_HOST 26 26 100.00
SPI_DEVICE/1R1W 31 33 93.94
SRAM_CTRL/MAIN 30 31 96.77
SRAM_CTRL/RET 30 31 96.77
UART 27 27 100.00
AC_RANGE_CHECK 18 19 94.74
ALERT_HANDLER 21 26 80.77
CLKMGR 26 27 96.30
GPIO 27 28 96.43
OTP_CTRL 27 30 90.00
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 19 19 100.00
XBAR_MAIN 18 18 100.00
XBAR_PERI 18 18 100.00
XBAR_DBG 18 18 100.00
XBAR_MBX 18 18 100.00
CHIP 77 247 31.17