TOP_DARJEELING_BATCH_SIM Simulation Results (Summary)

Monday October 20 2025 16:04:01 UTC

GitHub Revision: cf33148

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
AES/UNMASKED 31 32 96.88
AES/MASKED 31 32 96.88
AON_TIMER 23 23 100.00
CSRNG 19 19 100.00
DMA 24 25 96.00
EDN 21 21 100.00
ENTROPY_SRC/RNG_16BITS 22 22 100.00
HMAC 28 28 100.00
I2C 42 50 84.00
KEYMGR 30 30 100.00
KEYMGR_DPE 13 14 92.86
KMAC/MASKED 39 40 97.50
KMAC/UNMASKED 39 40 97.50
LC_CTRL/VOLATILE_UNLOCK_DISABLED 39 39 100.00
LC_CTRL/VOLATILE_UNLOCK_ENABLED 39 39 100.00
MBX 13 16 81.25
OTBN 19 41 46.34
PRIM_ALERT 5 5 100.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 18 19 94.74
ROM_CTRL/64KB 18 19 94.74
RV_DM/USE_DMI_INTERFACE 40 53 75.47
RV_TIMER 16 19 84.21
SPI_HOST 25 26 96.15
SPI_DEVICE/1R1W 31 33 93.94
SRAM_CTRL/MAIN 30 31 96.77
SRAM_CTRL/RET 30 31 96.77
UART 26 27 96.30
AC_RANGE_CHECK 20 20 100.00
ALERT_HANDLER 25 26 96.15
CLKMGR 24 27 88.89
GPIO 27 28 96.43
OTP_CTRL 19 30 63.33
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 19 19 100.00
XBAR_MAIN 18 18 100.00
XBAR_PERI 18 18 100.00
XBAR_DBG 18 18 100.00
XBAR_MBX 18 18 100.00
CHIP 79 250 31.60