TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Wednesday September 17 2025 17:00:31 UTC

GitHub Revision: 30ac532

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
ADC_CTRL 8 25 32.00
AES/UNMASKED 3 32 9.38
AES/MASKED 3 32 9.38
AON_TIMER 20 23 86.96
CSRNG 2 19 10.53
EDN 17 21 80.95
ENTROPY_SRC/RNG_4BITS 1 22 4.55
HMAC 16 28 57.14
I2C 37 50 74.00
KEYMGR 25 30 83.33
KMAC/MASKED 36 40 90.00
KMAC/UNMASKED 34 40 85.00
LC_CTRL/VOLATILE_UNLOCK_DISABLED 37 39 94.87
LC_CTRL/VOLATILE_UNLOCK_ENABLED 33 39 84.62
OTBN 3 41 7.32
PATTGEN 0 18 0.00
PRIM_ALERT 5 5 100.00
PRIM_ESC 0 1 0.00
PRIM_LFSR 3 4 75.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 16 19 84.21
ROM_CTRL/64KB 17 19 89.47
RV_DM/USE_JTAG_INTERFACE 23 53 43.40
RV_TIMER 18 19 94.74
SPI_HOST 5 26 19.23
SPI_DEVICE/1R1W 11 33 33.33
SPI_DEVICE/2P 21 33 63.64
SRAM_CTRL/MAIN 27 31 87.10
SRAM_CTRL/RET 27 31 87.10
SYSRST_CTRL 8 27 29.63
UART 25 27 92.59
USBDEV 81 100 81.00
GPIO 26 27 96.30
ALERT_HANDLER 21 26 80.77
CLKMGR 14 27 51.85
FLASH_CTRL 59 78 75.64
OTP_CTRL 0 30 0.00
PWM 0 17 0.00
PWRMGR 12 28 42.86
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 18 19 94.74
XBAR_MAIN 18 18 100.00
XBAR_PERI 17 18 94.44
CHIP 173 325 53.23