TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Monday September 22 2025 19:22:52 UTC

GitHub Revision: b7bab30

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
ADC_CTRL 25 25 100.00
AES/UNMASKED 3 32 9.38
AES/MASKED 3 32 9.38
AON_TIMER 20 23 86.96
CSRNG 1 19 5.26
EDN 8 21 38.10
ENTROPY_SRC/RNG_4BITS 2 22 9.09
HMAC 27 28 96.43
I2C 40 50 80.00
KEYMGR 29 30 96.67
KMAC/MASKED 36 40 90.00
KMAC/UNMASKED 35 40 87.50
LC_CTRL/VOLATILE_UNLOCK_DISABLED 19 39 48.72
LC_CTRL/VOLATILE_UNLOCK_ENABLED 38 39 97.44
OTBN 0 41 0.00
PATTGEN 4 18 22.22
PRIM_ALERT 2 5 40.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 2 4 50.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 18 19 94.74
ROM_CTRL/64KB 0 19 0.00
RV_DM/USE_JTAG_INTERFACE 43 53 81.13
RV_TIMER 16 19 84.21
SPI_HOST 2 26 7.69
SPI_DEVICE/1R1W 30 33 90.91
SPI_DEVICE/2P 10 33 30.30
SRAM_CTRL/MAIN 19 31 61.29
SRAM_CTRL/RET 26 31 83.87
SYSRST_CTRL 24 27 88.89
UART 23 27 85.19
USBDEV 93 100 93.00
GPIO 26 27 96.30
ALERT_HANDLER 22 26 84.62
CLKMGR 25 27 92.59
FLASH_CTRL 39 78 50.00
OTP_CTRL 14 30 46.67
PWM 0 17 0.00
PWRMGR 9 28 32.14
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 19 19 100.00
XBAR_MAIN 15 18 83.33
XBAR_PERI 18 18 100.00
CHIP 22 325 6.77