TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Tuesday October 14 2025 19:33:36 UTC

GitHub Revision: 0fc384d

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
ADC_CTRL 25 25 100.00
AES/UNMASKED 31 32 96.88
AES/MASKED 30 32 93.75
AON_TIMER 23 23 100.00
CSRNG 19 19 100.00
EDN 21 21 100.00
ENTROPY_SRC/RNG_4BITS 22 22 100.00
HMAC 28 28 100.00
I2C 42 50 84.00
KEYMGR 30 30 100.00
KMAC/MASKED 39 40 97.50
KMAC/UNMASKED 40 40 100.00
LC_CTRL/VOLATILE_UNLOCK_DISABLED 38 39 97.44
LC_CTRL/VOLATILE_UNLOCK_ENABLED 37 39 94.87
OTBN 18 41 43.90
PATTGEN 15 18 83.33
PRIM_ALERT 5 5 100.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 19 19 100.00
ROM_CTRL/64KB 18 19 94.74
RV_DM/USE_JTAG_INTERFACE 44 53 83.02
RV_TIMER 15 19 78.95
SPI_HOST 26 26 100.00
SPI_DEVICE/1R1W 31 33 93.94
SPI_DEVICE/2P 33 33 100.00
SRAM_CTRL/MAIN 29 31 93.55
SRAM_CTRL/RET 28 31 90.32
SYSRST_CTRL 26 27 96.30
UART 26 27 96.30
USBDEV 98 100 98.00
GPIO 26 27 96.30
ALERT_HANDLER 25 26 96.15
CLKMGR 26 27 96.30
FLASH_CTRL 59 78 75.64
OTP_CTRL 25 30 83.33
PWM 8 17 47.06
PWRMGR 9 28 32.14
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 19 19 100.00
XBAR_MAIN 18 18 100.00
XBAR_PERI 18 18 100.00
CHIP 280 326 85.89