TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Saturday February 08 2025 23:09:58 UTC

GitHub Revision: c12958f63b

Branch: master

Name Passing Total Pass Rate Coverage
TL_AGENT 50 50 100.00 --
ADC_CTRL 886 920 96.30 97.55
AES/UNMASKED 1510 1602 94.26 97.23
AES/MASKED 1529 1602 95.44 98.39
AON_TIMER 480 480 100.00 98.20
CSRNG 1613 1630 98.96 97.78
EDN 1112 1130 98.41 95.95
ENTROPY_SRC 2087 2570 81.21 97.12
GPIO 970 970 100.00 98.05
HMAC 990 990 100.00 90.08
I2C 1845 2042 90.35 88.72
KEYMGR 1009 1110 90.90 97.78
KMAC/MASKED 902 940 95.96 95.14
KMAC/UNMASKED 898 940 95.53 93.73
LC_CTRL/VOLATILE_UNLOCK_DISABLED 1000 1030 97.09 90.30
LC_CTRL/VOLATILE_UNLOCK_ENABLED 999 1030 96.99 90.41
OTBN 572 585 97.78 99.07
PATTGEN 521 570 91.40 98.96
PRIM_ALERT 79 80 98.75 95.19
PRIM_ESC 20 20 100.00 92.29
PRIM_LFSR 200 200 100.00 98.31
PRIM_PRESENT 50 50 100.00 93.41
PRIM_PRINCE 500 500 100.00 100.00
PWM 255 276 92.39 99.02
ROM_CTRL/32KB 447 460 97.17 99.58
ROM_CTRL/64KB 458 460 99.57 99.60
RV_DM/USE_JTAG_INTERFACE 423 483 87.58 76.26
RV_TIMER 577 620 93.06 99.66
SPI_HOST 827 840 98.45 96.78
SPI_DEVICE/1R1W 1130 1151 98.18 93.24
SPI_DEVICE/2P 1150 1151 99.91 93.27
SRAM_CTRL/MAIN 1190 1190 100.00 98.20
SRAM_CTRL/RET 1188 1190 99.83 98.19
SYSRST_CTRL 905 932 97.10 97.67
UART 1316 1320 99.70 98.83
USBDEV 3904 3965 98.46 97.09
ALERT_HANDLER 813 850 95.65 99.21
CLKMGR 792 960 82.50 98.04
FLASH_CTRL 1247 1281 97.35 94.95
OTP_CTRL 1199 1343 89.28 94.42
PWRMGR 980 1120 87.50 98.00
RSTMGR_CNSTY_CHK 10 10 100.00 95.87
RSTMGR 619 620 99.84 99.46
XBAR_MAIN 900 900 100.00 99.19
XBAR_PERI 900 900 100.00 99.19
CHIP 2849 2955 96.41 95.88