TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Sunday March 23 2025 00:10:17 UTC

GitHub Revision: 27fc640f8d

Branch: master

Name Passing Total Pass Rate Coverage
TL_AGENT 50 50 100.00 --
ADC_CTRL 891 920 96.85 97.56
AES/UNMASKED 1519 1602 94.82 97.31
AES/MASKED 1531 1602 95.57 98.36
AON_TIMER 314 315 99.68 95.76
CSRNG 1611 1630 98.83 97.79
EDN 1108 1130 98.05 95.84
ENTROPY_SRC 2029 2570 78.95 97.12
HMAC 1060 1061 99.91 --
I2C 1853 2042 90.74 88.01
KEYMGR 987 1110 88.92 97.78
KMAC/MASKED 895 940 95.21 95.32
KMAC/UNMASKED 884 940 94.04 93.62
LC_CTRL/VOLATILE_UNLOCK_DISABLED 952 1030 92.43 90.25
LC_CTRL/VOLATILE_UNLOCK_ENABLED 956 1030 92.82 90.39
OTBN 564 585 96.41 98.97
PATTGEN 491 570 86.14 98.88
PRIM_ALERT 78 80 97.50 95.19
PRIM_ESC 20 20 100.00 92.29
PRIM_LFSR 200 200 100.00 98.31
PRIM_PRESENT 50 50 100.00 93.41
PRIM_PRINCE 500 500 100.00 100.00
PWM 255 276 92.39 98.90
ROM_CTRL/32KB 393 460 85.43 99.65
ROM_CTRL/64KB 404 460 87.83 99.63
RV_DM/USE_JTAG_INTERFACE 419 483 86.75 76.30
RV_TIMER 581 620 93.71 99.80
SPI_HOST 824 840 98.10 96.33
SPI_DEVICE/1R1W 1130 1151 98.18 94.43
SPI_DEVICE/2P 1149 1151 99.83 94.47
SRAM_CTRL/MAIN 1179 1190 99.08 96.87
SRAM_CTRL/RET 1176 1190 98.82 96.82
SYSRST_CTRL 910 932 97.64 97.06
UART 1314 1320 99.55 97.77
USBDEV 3900 3965 98.36 97.11
GPIO 970 1020 95.10 98.85
ALERT_HANDLER 803 850 94.47 99.19
CLKMGR 903 960 94.06 98.16
FLASH_CTRL 954 1281 74.47 94.93
OTP_CTRL 779 1343 58.00 93.41
PWRMGR 972 1120 86.79 98.00
RSTMGR_CNSTY_CHK 10 10 100.00 95.87
RSTMGR 618 620 99.68 99.49
XBAR_MAIN 900 900 100.00 99.17
XBAR_PERI 900 900 100.00 99.20
CHIP 1879 2955 63.59 84.94