TOP_DARJEELING_BATCH_SIM Simulation Results (Summary)

Thursday June 05 2025 17:03:55 UTC

GitHub Revision: 7592556

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
AES/UNMASKED 30 32 93.75
AES/MASKED 31 32 96.88
AON_TIMER 23 23 100.00
CSRNG 17 19 89.47
DMA 21 21 100.00
EDN 20 21 95.24
HMAC 28 28 100.00
I2C 45 50 90.00
KEYMGR 27 30 90.00
KEYMGR_DPE 14 14 100.00
KMAC/MASKED 40 40 100.00
KMAC/UNMASKED 36 40 90.00
LC_CTRL/VOLATILE_UNLOCK_DISABLED 39 39 100.00
LC_CTRL/VOLATILE_UNLOCK_ENABLED 39 39 100.00
MBX 10 14 71.43
OTBN 41 41 100.00
PRIM_ALERT 4 4 100.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 19 19 100.00
ROM_CTRL/64KB 19 19 100.00
RV_DM/USE_DMI_INTERFACE 41 53 77.36
RV_TIMER 19 19 100.00
SPI_HOST 25 26 96.15
SPI_DEVICE/1R1W 31 33 93.94
SRAM_CTRL/MAIN 30 31 96.77
SRAM_CTRL/RET 29 31 93.55
UART 26 27 96.30
AC_RANGE_CHECK 14 18 77.78
ALERT_HANDLER 21 26 80.77
CLKMGR 26 27 96.30
GPIO 26 28 92.86
OTP_CTRL 27 30 90.00
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 19 19 100.00
XBAR_MAIN 18 18 100.00
XBAR_PERI 18 18 100.00
XBAR_DBG 18 18 100.00
XBAR_MBX 18 18 100.00
CHIP 76 247 30.77