TOP_DARJEELING_BATCH_SIM Simulation Results (Summary)

Thursday September 04 2025 16:03:40 UTC

GitHub Revision: 72c264a

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
AES/UNMASKED 31 32 96.88
AES/MASKED 31 32 96.88
AON_TIMER 23 23 100.00
CSRNG 19 19 100.00
DMA 24 25 96.00
EDN 20 21 95.24
ENTROPY_SRC/RNG_16BITS 21 22 95.45
HMAC 28 28 100.00
I2C 43 50 86.00
KEYMGR 30 30 100.00
KEYMGR_DPE 14 14 100.00
KMAC/MASKED 40 40 100.00
KMAC/UNMASKED 40 40 100.00
LC_CTRL/VOLATILE_UNLOCK_DISABLED 39 39 100.00
LC_CTRL/VOLATILE_UNLOCK_ENABLED 39 39 100.00
MBX 13 16 81.25
OTBN 40 41 97.56
PRIM_ALERT 5 5 100.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 19 19 100.00
ROM_CTRL/64KB 19 19 100.00
RV_DM/USE_DMI_INTERFACE 39 53 73.58
RV_TIMER 19 19 100.00
SPI_HOST 26 26 100.00
SPI_DEVICE/1R1W 31 33 93.94
SRAM_CTRL/MAIN 30 31 96.77
SRAM_CTRL/RET 30 31 96.77
UART 26 27 96.30
AC_RANGE_CHECK 19 20 95.00
ALERT_HANDLER 22 26 84.62
CLKMGR 24 27 88.89
GPIO 27 28 96.43
OTP_CTRL 18 30 60.00
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 19 19 100.00
XBAR_MAIN 18 18 100.00
XBAR_PERI 18 18 100.00
XBAR_DBG 18 18 100.00
XBAR_MBX 18 18 100.00
CHIP 81 250 32.40