TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Thursday April 17 2025 20:22:04 UTC

GitHub Revision: 91d1222

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
ADC_CTRL 24 25 96.00
AES/UNMASKED 31 32 96.88
AES/MASKED 31 32 96.88
AON_TIMER 23 23 100.00
CSRNG 18 19 94.74
EDN 20 21 95.24
ENTROPY_SRC 17 22 77.27
HMAC 28 28 100.00
I2C 46 50 92.00
KEYMGR 27 30 90.00
KMAC/MASKED 39 40 97.50
KMAC/UNMASKED 39 40 97.50
LC_CTRL/VOLATILE_UNLOCK_DISABLED 38 39 97.44
LC_CTRL/VOLATILE_UNLOCK_ENABLED 38 39 97.44
OTBN 39 41 95.12
PATTGEN 15 18 83.33
PRIM_ALERT 4 4 100.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 19 19 100.00
ROM_CTRL/64KB 19 19 100.00
RV_DM/USE_JTAG_INTERFACE 48 53 90.57
RV_TIMER 15 16 93.75
SPI_HOST 25 26 96.15
SPI_DEVICE/1R1W 31 33 93.94
SPI_DEVICE/2P 31 33 93.94
SRAM_CTRL/MAIN 28 31 90.32
SRAM_CTRL/RET 29 31 93.55
SYSRST_CTRL 27 27 100.00
UART 27 27 100.00
USBDEV 97 99 97.98
GPIO 26 27 96.30
ALERT_HANDLER 23 26 88.46
CLKMGR 25 27 92.59
FLASH_CTRL 56 78 71.79
OTP_CTRL 27 30 90.00
PWM 8 17 47.06
PWRMGR 28 28 100.00
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 19 19 100.00
XBAR_MAIN 18 18 100.00
XBAR_PERI 18 18 100.00
CHIP 286 325 88.00