TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Thursday June 05 2025 20:26:30 UTC

GitHub Revision: 7592556

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
ADC_CTRL 25 25 100.00
AES/UNMASKED 30 32 93.75
AES/MASKED 30 32 93.75
AON_TIMER 23 23 100.00
CSRNG 18 19 94.74
EDN 21 21 100.00
ENTROPY_SRC 19 22 86.36
HMAC 28 28 100.00
I2C 45 50 90.00
KEYMGR 26 30 86.67
KMAC/MASKED 39 40 97.50
KMAC/UNMASKED 36 40 90.00
LC_CTRL/VOLATILE_UNLOCK_DISABLED 38 39 97.44
LC_CTRL/VOLATILE_UNLOCK_ENABLED 39 39 100.00
OTBN 41 41 100.00
PATTGEN 14 18 77.78
PRIM_ALERT 4 4 100.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 19 19 100.00
ROM_CTRL/64KB 19 19 100.00
RV_DM/USE_JTAG_INTERFACE 47 53 88.68
RV_TIMER 19 19 100.00
SPI_HOST 26 26 100.00
SPI_DEVICE/1R1W 31 33 93.94
SPI_DEVICE/2P 33 33 100.00
SRAM_CTRL/MAIN 30 31 96.77
SRAM_CTRL/RET 29 31 93.55
SYSRST_CTRL 27 27 100.00
UART 26 27 96.30
USBDEV 97 99 97.98
GPIO 26 27 96.30
ALERT_HANDLER 22 26 84.62
CLKMGR 26 27 96.30
FLASH_CTRL 58 78 74.36
OTP_CTRL 27 30 90.00
PWM 8 17 47.06
PWRMGR 28 28 100.00
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 19 19 100.00
XBAR_MAIN 18 18 100.00
XBAR_PERI 18 18 100.00
CHIP 284 325 87.38